Guy Lemieux's Publications

Last modified: probably on or after June 24, 2012.
My home page
My conference acceptance rates page

Google Scholar Profile

This page ordered by publication type


    Machine Learning

  1. D. Yang, A. Ghasemazar, X. Ren, M. Golub, G. Lemieux, M. Lis
    ``Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training'',
    IEEE/ACM International Symposium on Microarchitecture (MICRO), October, 2020.
    see also arxiv.org

  2. M. Golub, G. Lemieux, M. Lis
    ``Full Deep Neural Network Training on a Pruned Weight Budget'',
    Conference on Systems and Machine Learning (SysML), April, 2019.
    see also arxiv.org
    presentation

  3. Maximilian Golub ``DropBack: Continuous Pruning During Deep Neural Network Training'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, August 2018.
    UBC link

  4. Joseph Edwards ``Real-time Computer Vision in Software using Custom Vector Overlays'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, July 2018.
    UBC link

  5. J. Edwards, G. G.F. Lemieux
    ``Real-time Object Detection in Software with Custom Vector Instructions and Algorithm Changes'',
    IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), July, 2017.
    presentation

  6. G. G.F. Lemieux, Joe Edwards, Joel Vandergriendt, Aaron Severance, Ryan De Iaco, Abdullah Raouf, Hussein Osman, Tom Watzka, Satwant Singh,
    ``TinBiNN: Tiny Binarized Neural Network Overlay in about 5,000 4-LUTs and 5mW'',
    International Workshop on Overlay Architectures for FPGAs (OLAF), February, 2017.
    presentation



    Computer Vision (with Overlays!)

  7. H. Omidian, G. G.F. Lemieux
    ``Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration'',
    International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), June, 2019.

  8. H. Omidian, N. Ivanov, G. G.F. Lemieux
    ``An Accelerated OpenVX Overlay for Pure Software Programmers'',
    International Conference on Field-Programmable Technology (ICFPT), December, 2018.
    presentation

  9. Hossein Omidian Savarbaghi ``Automated Space/Time Scaling of Streaming Task Graphs on Field-Programmable Gate Arrays'',
    Ph.D. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, October 2018.
    UBC link

  10. H. Omidian, G. G.F. Lemieux
    ``JANUS: A Compilation System for Balancing Parallelism and Performance in OpenVX'',
    International Conference on Machine Vision and Information Technology (CMVIT), February, 2018.
    presentation

  11. H. Omidian, G. G.F. Lemieux
    ``Exploring Automated Space/Time Tradeoffs for OpenVX Compute Graphs'',
    International Conference on Field-Programmable Technology (ICFPT), December, 2017.
    presentation



    FPGA Overlays

  12. Y. Serhan Gener, P. Newton, D. Tan, S. Richelson, G. Lemieux, P. Brisk
    ``An FPGA-based Programmable Vector Engine for Fast Fully Homomorphic Encryption over the Torus'',
    Secure and Private Systems for Machine Learning Workshop (SPSL), June, 2021.

  13. H. Omidian, G. G.F. Lemieux
    ``Automated Space/Time Scaling of Streaming Task Graph'',
    International Workshop on Overlay Architectures for FPGAs (OLAF), February, 2016.
    presentation

  14. Keith Lee. ``The DEVBOX development environment: an environment for introducing Verilog to young students'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, January 2016.
    video demo UBC link

  15. Xi (Michael) Yue. ``Rapid Overlay Builder for Xilinx FPGAs'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, November 2014.
    presentation UBC link

  16. M. Yue, D. Koch, G. G.F. Lemieux
    ``Rapid Overlay Builder for Xilinx FPGAs'',
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May, 2015.
    presentation

  17. D. Koch, C. Beckhoff, G. Lemieux
    ``An Efficient FPGA Overlay for Portable Custom Instruction Set Extensions'',
    International Conference on Field-Programmable Logic and Applications (FPL), September, 2013.
    presentation

  18. A. Brant, A. Abdelhadi, D. Sim, T. Tang, M. Yue, G. Lemieux
    ``Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor'',
    IEEE International Conference on Field-Programmable Custom Computing Machines (FCCM), April, 2013.
    presentation
    example of overclocking disaster on youtube.com

  19. A. Brant ``Coarse and Fine Grain Programmable Overlay Architectures for FPGAs'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, November 2012.
    presentation UBC link

  20. A. Brant, G. Lemieux
    ``ZUMA: An Open FPGA Overlay Architecture'',
    IEEE International Symposium on Field-Programmable Custom Computing Machines, May 2012, pp. 93-96.
    poster

    for more overlays, see also work below on vector processors and the MALIBU CGRA



    FPGA Computer Architecture

  21. M. Young, A. J. Hu, G. G.F. Lemieux
    ``Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators'',
    ACM Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June, 2021.

  22. A. Abdelhadi, G. G.F. Lemieux, L. Shannon
    ``Modular Block-RAM-based Longest-Prefix Match Ternary Content-Addressable Memories'',
    International Conference on Field-Programmable Logic and Applications (FPL), August, 2018.
    presentation

  23. A. Abdelhadi, G. G.F. Lemieux
    ``Modular Switched Multi-ported SRAM-based Memories'',
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), September, 2016, 27 pages.
    GitHub code,
    http://doi.org/10.1145/2851506

  24. A. Abdelhadi, G. G.F. Lemieux
    ``Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs'',
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May, 2016.
    presentation

  25. A. Abdelhadi, G. G.F. Lemieux
    ``Modular SRAM-based Binary Content-Addressable Memories'',
    IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May, 2015.
    presentation

  26. Aaron Severance ``Broadening the Applicability of FPGA-based Soft Vector Processors'',
    Ph.D. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, March 2015.
    UBC link

  27. A. Severance, J. Edwards, G. Lemieux
    ``Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors'',
    International Symposium on Field-Programmable Gate Arrays (FPGA), February, 2015.
    presentation

  28. A. Abdelhadi, G. G.F. Lemieux
    ``Deep and Narrow Binary Content-Addressable Memories using FPGA-based BRAMs'',
    International Conference on Field-Programmable Technology (FPT), December, 2014.
    presentation

  29. A. Abdelhadi, G. G.F. Lemieux
    ``Modular Multi-ported SRAM-based Memories'',
    International Symposium on Field-Programmable Gate Arrays (FPGA), February, 2014.
    presentation

  30. A. Severance, J. Edwards, H. Omidian, G. Lemieux
    ``Soft Vector Processors with Streaming Pipelines'',
    International Symposium on Field-Programmable Gate Arrays (FPGA), February, 2014.
    presentation

  31. A. Severance, G. Lemieux
    ``Embedded Supercomputing in FPGAs with the VectorBlox MXP Matrix Processor'',
    International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September, 2013.
    presentation

  32. A. Severance, G. Lemieux
    ``TputCache: High-Frequency, Multi-Way Cache for High-Throughput FPGA Applications'',
    International Conference on Field-Programmable Logic and Applications (FPL), September, 2013.
    presentation

  33. A. Severance, G. Lemieux,
    ``VENICE: A Compact Vector Processor for FPGA Applications'',
    IEEE International Conference on Field-Programmable Technology (FPT), December, 2012.
    presentation

  34. A. Brant, A. Abdelhadi, A. Severance, G. Lemieux,
    ``Pipeline Frequency Boosting: Hiding Dual-Ported Block RAM Latency using Intentional Clock Skew'',
    IEEE International Conference on Field-Programmable Technology (FPT), December, 2012.
    presentation

  35. Z. Liu. ``Accelerator Compiler for the VENICE Vector Processor'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, September 2012.
    presentation UBC link

  36. A. Severance, G. Lemieux,
    ``VENICE: A Compact Vector Processor for FPGA Applications'',
    Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL), June 2012.
    presentation

  37. Z. Liu, A. Severance, S. Sing, G. Lemieux,
    ``Accelerator Compiler for the VENICE Vector Processor'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays, February 2012, pp. 229-232.
    presentation

  38. David Grant ``CAD Algorithms and Performance of Malibu: An FPGA with Time-Multiplexed Coarse-Grained Elements'',
    P.h.D. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, August 2011.
    presentation UBC link

  39. A. Severance, G. Lemieux,
    ``VENICE: A Compact Vector Processor for FPGA Applications'',
    HotChips 2011, August 2011. (poster)

  40. C. Chou, A. Severance, A. Brant, Z. Liu, S. Sant, G. Lemieux,
    ``VEGAS: Soft Vector Processor with Scratchpad Memory'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays, February 2011, pp. 15-24.
    presentation

  41. D. Grant, C. Wang, G. Lemieux,
    ``A CAD Framework for MALIBU: An FPGA with Time-Multiplexed Coarse-Grained Elements'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays, February 2011, pp. 123-122.
    presentation

  42. D. Grant, G. Smecher, G. Lemieux, R. Francis,
    ``Rapid Synthesis and Simulation of Computational Circuits in an MPPA'',
    Springer Journal of Signal Processing, published online 15 December, 2010, 14 pages.
    http://dx.doi.org/10.1007/s11265-010-0562-x

  43. C. H.-Y. Chou. ``VIPERS II : A Soft-core Vector Processor with Single-copy Scratchpad Memory'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, April 2010.
    presentation UBC link

  44. D. Grant, G. Smecher, R. Francis, G. Lemieux,
    ``Rapid Synthesis and Simulation of Computational Circuits in an MPPA'',
    IEEE International Conference on Field-Programmable Technology, December, 2009, pp. 151-158.
    Please consult the journal paper version for the latest details.
    presentation

  45. D. Grant, G. Lemieux, ``A Spatial Computing Architecture for Implementing Computational Circuits'',
    CMC Microsystems and Nanoelectronics Research Conference, Ottawa, pp. 41-44, October 2008.
    Bronze Leaf Certificate Paper Award.
    presentation

  46. J. Yu, C. Eagleston, C. H.-Y. Chou, M. Perreault, G. Lemieux,
    ``Vector Processing as a Soft Processor Accelerator'',
    ACM Transactions on Reconfigurable Technology and Systems, 2(2), June 2009, 34 pages.
    http://dx.doi.org/10.1145/1534916.1534922

  47. J. Yu, ``Vector Processing as a Soft-CPU Accelerator'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, May 2008.
    presentation

  48. J. Yu, G. Lemieux, C. Eagleston, ``Vector Processing as a Soft-core CPU Accelerator'',
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, pp. 222-231, February 2008.
    Please consult the journal paper submission for the latest, corrected details.
    presentation

  49. J. Yu, G. Lemieux, ``A Case for Soft Vector Processors in FPGAs'', refereed poster
    IEEE International Conference on Field-Programmable Technology, Kitakyushu, Japan, December 2007, pp. 341-344.
    presentation



    FPGA Configuration Storage

  50. A. Abdelhadi, G. Lemieux,
    ``Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations'',
    International Conference on ReConFigurable Computing and FPGAs, December 2011, pp. 20-26.
    presentation



    Structured ASICs

  51. Usman Ahmed ``Impact of custom interconnect masks on cost and performance of structured ASICs'',
    P.h.D. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, April 2011.
    presentation UBC link

  52. U. Ahmed, G. Lemieux, S. Wilton,
    ``Performance and Cost Trade-offs in Metal-Programmable Structured ASICs (MPSAs)'',
    IEEE Transactions on Very-Large Scale Integration Systems, published online 17 October 2010, 14 pages.
    http://dx.doi.org/10.1109/TVLSI.2010.2076841

  53. U. Ahmed, G. Lemieux, S. Wilton,
    ``The Impact of Interconnect Architecture on Via-Programmable Structured ASICs (VPSAs)'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays, February 2010, pp. 263-272.
    presentation

  54. U. Ahmed, G. Lemieux, S. Wilton,
    ``Area, Delay, Power, and Cost Trends for Metal-Programmable Structured ASICs (MPSAs)''    ,
    IEEE International Conference on Field-Programmable Technology, December 2009, pp. 278-284. (poster/short paper)
    Please consult the journal paper version for the latest details.
    presentation

  55. T. Fujino, T. Nishimoto, Y. Kokusyo, M. Yoshikawa, G. Lemieux,
    ``Via-Programmable Logic Array VPEX2 with Configurable DFF using 2 Logic Elements'',
    International Symposium on Integrated Circuits, December 2009, pp. 21-24.

  56. K. Kitamura, S. Yamada, M. Kawarasaki, Y. Kokusyou, U. Ahmed, G. Lemieux, M. Yoshikawa, T. Fujino,
    ``Interconnect Utilization of VPEX Via-programmable Structured ASIC'',
    Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), March, 2009, 5 pages.



    Interconnection Network Circuit Design

  57. P. Teehan, G. Lemieux, M. Greenstreet,
    ``Estimating Reliability and Throughput of Source-synchronous Wave-pipelined Interconnect'',
    ACM/IEEE International Symposium on Networks-on-Chip, San Diego, California, pp. 234-243, May 2009.
    presentation

  58. P. Teehan, G. Lemieux, M. Greenstreet, ``Towards Reliable 5Gbps Wave-pipelined and 3Gbps Surfing Interconnect in 65nm FPGAs'',
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, pp. 43-52, February 2009.
    presentation

  59. P. Teehan, ``Reliable High-throughput FPGA Interconnect using Source-synchronous Surfing and Wave Pipelining'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, October 2008.
    presentation

  60. V. Aken'ova, G. Lemieux, R. Saleh, ``Soft++: An Improved Embedded FPGA Methodology for SoC Designs'',
    accepted to appear IEEE Transactions on VLSI, 2007.

  61. E. Lee, G. Lemieux, S. Mirabbasi, ``Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays'',
    Journal of Signal Processing Systems, Springer, 51(1), April 2008.
    http://dx.doi.org/10.1007/s11265-007-0141-y

  62. E. Lee, G. Lemieux, S. Mirabbasi, ``Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays'',
    IEEE International Conference on Field-Programmable Technology, Bangkok, pp. 89-96, December 2006.
    Please consult the journal paper for the latest details.
    presentation

  63. E. Lee, ``Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, June 2006.
    presentation

  64. V. Aken'Ova, G. Lemieux, R. Saleh, ``An Improved Soft eFPGA Design and Implementation Strategy'',
    Custom Integrated Circuits Conference, San Jose, California, pp. 179-182, September 2005.
    presentation

  65. V. Aken'Ova, ``Bridging the Gap between Soft and Hard eFPGA Design'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, March 2005.

  66. G. Lemieux, E. Lee, M. Tom, and A. Yu, ``Directional and Single-Driver Wires in FPGA Interconnect'',
    IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, pp. 41-48, December 2004.
    Best Paper Award.
    presentation

  67. G. Lemieux, D. Lewis, ``Circuit Design of FPGA Routing Switches'',
    ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 19-28, February 2002.
    presentation (HTML only)



    Interconnection Network Generation, Analysis, Estimation (Topologies)

  68. Z. Zhou, Z. Zhu, J. Chen, Y. Ma, B. Yu, T.Y. Ho, G. G.F. Lemieux, A. Ivanov
    ``Congestion-aware Global Routing using Deep Convolutional Generative Adversarial Networks'',
    International Workshop on Machine Learning for CAD (MLCAD), September, 2019.

  69. Y. Moctar, N. George, H. Afshar, P. Ienne, G. Lemieux, P. Brisk,
    ``Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012, pp. 255-264.
    presentation

  70. D. Yeager, D. Chiu, G. Lemieux, ``Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction'',
    International Workshop on System-Level Interconnect Prediction, Austin, TX, March 2007.
    This PDF version is a corrected, most-up-to-date copy.
    presentation

  71. G. Lemieux, D. Lewis, ``Design of Interconnection Networks for Programmable Logic'', Springer (formerly Kluwer Academic Publishers), 2004.

  72. G. Lemieux, ``Efficient Interconnection Network Components for Programmable Logic Devices'',
    Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, November 2003.
    Available as a book.

  73. G. Lemieux, D. Lewis, ``Analytical Framework for Switch Block Design'',
    Field-Programmable Logic and Applications, La Grande Motte, France, pp. 122-131, September 2002.
    presentation

  74. G. Lemieux, D. Lewis, ``Checkerboard Switch Block Topologies for Routing Diversity'',
    poster at ACM/SIGDA International Symposium on FPGAs, Monterey, CA, February 2002.
    presentation (HTML only)

  75. G. Lemieux, D. Lewis, ``Using Sparse Crossbars within LUT Clusters'',
    ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 59-68, February 2001.

  76. G. Lemieux, P. Leventis, D. Lewis, ``Generating Highly-Routable Sparse Crossbars for PLDs'',
    ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 155-164, February 2000.



    FPGA Power Reduction

  77. J. Lamoureux, G. Lemieux, S. Wilton,
    ``GlitchLess: Dynamic Power Minimization in FPGAs through Edge Alignment and Glitch Filtering'',
    IEEE Transactions on VLSI, November, 2008, pp. 1521-1534.
    http://dx.doi.org/10.1109/TVLSI.2008.2001237

  78. J. Lamoureux, G. Lemieux, S. Wilton, ``GlitchLess: An Active Glitch Minimization Technique for FPGAs'',
    ACM/SIGDA International Symposium on FPGAs, Monterey, CA, February 2007.
    Please consult the journal paper for the latest details.
    presentation



    Parallel FPGA CAD Algorithms

  79. J. Goeders, G. Lemieux, S. Wilton,
    ``Deterministic Timing-Driven Parallel Placement by Simulated Annealing using Half-Box Window Decomposition'',
    International Conference on ReConFigurable Computing and FPGAs, December 2011, pp. 41-48.
    Best Paper Nominee.
    presentation

  80. C. Wang. ``Scalable and Deterministic Timing-driven Parallel Placement for FPGAs'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, October 2011.
    presentation UBC link

  81. C. Wang, G. Lemieux,
    ``Scalable and Deterministic Timing-Driven Parallel Placement for FPGAs'',
    ACM/IEEE International Symposium on Field-Programmable Gate Arrays, February 2011, pp. 153-162.
    Best Paper Nominee (top 3).
    presentation

  82. G. Smecher, S. Wilton, G. Lemieux,
    ``Self-Hosted Placement for Massively Parallel Processor Arrays'',
    IEEE International Conference on Field-Programmable Technology, December, 2009, pp. 159-166.
    presentation



    FPGA CAD

  83. H. Omidian, G. G.F. Lemieux
    ``Low-Level Loop Analysis and Pipelining of Applications mapped to Xilinx FPGAs'' (short paper),
    International Conference on Field-Programmable Logic and Applications (FPL), August, 2019.

  84. Y. Moctar, G. Lemieux, P. Brisk,
    ``Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays with Sparse Intra-cluster Routing Crossbars'',
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2015, 14 pages.
    http://dx.doi.org/10.1109/TCAD.2015.2445739

  85. Y. Moctar, G. Lemieux, P. Brisk,
    ``Routing Algorithms for FPGAs with Sparse Intra-Cluster Routing Crossbars'',
    International Conference on Field-Programmable Logic and Applications (FPL) , August 2012.
    presentation

  86. X. Dong, G. Lemieux,
    ``PGR: Period and Glitch Reduction via Clock Skew Scheduling, Delay Padding and GlitchLess'',
    IEEE International Conference on Field-Programmable Technology, December, 2009, pp. 88-95.
    presentation

  87. D. Chiu, G. Lemieux, S. Wilton,
    ``Congestion-Driven Regional Re-clustering for Low-Cost FPGAs'',
    IEEE International Conference on Field-Programmable Technology, December, 2009, pp. 167-174.
    presentation

  88. D. Leong, G. Lemieux,
    ``RePlace: An Incremental Placement Algorithm for Field-Programmable Gate Arrays'',
    International Conference on Field-Programmable Logic and Applications, Sept 2009, pp. 154-161.
    presentation

  89. X. Dong. ``Period and glitch reduction via clock skew scheduling, delay padding and glitchless'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, September 2009.
    presentation UBC link

  90. D. Chiu. ``Congestion-driven Re-clustering CAD Flow for Low-cost FPGAs'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, September 2009.
    presentation UBC link

  91. M. Yamashita ``A Combined Clustering and Placement Algorithm for FPGAs'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, November 2007.
    presentation

  92. D. Leong ``Incremental Placement for Field-Programmable Gate Arrays'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, November 2006.
    presentation

  93. M. Tom, D. Leong, G. Lemieux, ``Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs'',
    IEEE International Conference Computer-Aided Design, San Jose, November 2006.
    presentation

  94. M. Tom, ``Channel Width Reduction Techniques for System-on-Chip Circuits in Field-Programmable Gate Arrays'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, April 2006.
    presentation

  95. M. Tom, G. Lemieux, ``Logic Block Clustering of Large Designs for Channel-Width Constrained FPGAs'',
    ACM/SIGDA Design Automation Conference, Anaheim, California, pp. 726-731, June 2005.
    presentation download: data & software

  96. G. Lemieux, S. Brown, D. Vranesic, ``On Two-Step Routing for FPGAs''
    International Symposium on Physical Design, Napa, CA, pp. 60-66, April 1997.

  97. S. Brown, M. Khellah, and G. Lemieux, ``Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays'',
    Journal of VLSI Design, 4(4), pp. 275-291, 1996.
    http://dx.doi.org/10.1155/1996/45983

  98. G. Lemieux, ``Design and Implementation of Detailed Router Software for Segmented-Architecture Field-Programmable Gate Arrays'',
    B.A.Sc. Thesis, Division of Engineering Science, University of Toronto, June 1993.
    (download software and other options)

  99. G. Lemieux and S. Brown, ``A Detailed Router for Allocating Wire Segments in FPGAs'',
    ACM Physical Design Workshop, Lake Arrowhead, California, pp. 215-226, April 1993.



    Defect-Tolerant FPGAs

  100. A. Yu, G. Lemieux, ``Defect Tolerance: Impact of Granularity'',
    IEEE International Conference on Field-Programmable Technology, Singapore, pp. 189-196, December 2005.
    presentation

  101. A. Yu, G. Lemieux, ``Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement'',
    Int'l Conference on Field-Programmable Logic and Applications, Tampere, Finland, pp. 255-262, August 2005.
    presentation

  102. A. Yu, ``Defect Tolerance for Yield Enhancement of FPGA Interconnect Using Fine-grain and Coarse-grain Redundancy'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, August 2005.
    presentation



    Applications on FPGAs

  103. J. T.-L. Ho, ``PERG-Rx: an FPGA-based pattern-matching engine with limited regular expression support for large pattern databases'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, September 2009.
    presentation UBC link

  104. J. Ho, G. Lemieux, ``PERG-Rx: A Hardware Pattern-matching Engine Supporting Limited Regular Expressions'',
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, pp. 257-260, February 2009.
    presentation

  105. J. Ho, G. Lemieux, ``PERG: A Scalable FPGA-based Pattern-matching Engine with Consolidated Bloomier Filters'',
    IEEE International Conference on Field-Programmable Technology, Taipei, Taiwan, December 2008, pp. 73-80.
    presentation

  106. J. Ho, G. Lemieux, ``PERG: A Scalable Pattern-matching Accelerator'',
    CMC Microsystems and Nanoelectronics Research Conference, Ottawa, pp. 29-32, October 2008.
    presentation



    Logic Design for FPGAs

  107. Z. Zilic, G. Lemieux, K. Loveless, S. Brown, and Z. Vranesic ``Designing for High Speed-Performance in CPLDs and FPGAs''
    Proc. 3rd Canadian Workshop on Field-Programable Devices (FPD'95): Technology, Tools, and Applications, Montreal, Canada, pp. 108-113, May 1995.



    Artificial/Synthetic Circuit Generation

  108. D. Grant, G. Lemieux,
    ``Perturb+Mutate: Semi-Synthetic Circuit Generation for Incremental Placement and Routing'',
    ACM Transactions on Reconfigurable Technology and Systems, September 2008, 24 pages.
    http://dx.doi.org/10.1145/1391732.1391736

  109. D. Grant, G. Lemieux, ``Perturber: Semi-Synthetic Circuit Generation Using Ancestor Control for Testing Incremental Place and Route'',
    IEEE International Conference on Field-Programmable Technology, Bangkok, pp. 189-195, December 2006.
    Please consult the journal paper for the latest details.
    presentation

  110. D. Grant, S. Chin, G. Lemieux, ``Semi-synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Place and Route Tools'', poster at ACM/SIGDA International Symposium on Field-Programmable Logic, Madrid, August 2006.
    Please consult the journal paper for the latest details.



    GALS and SoC Design

  111. P. Teehan, M. Greenstreet, G. Lemieux, ``A Survey and Taxonomy of GALS Design Styles'',
    IEEE Design & Test of Computers, 24(5), Sept.-Oct., 2007, pp. 418-428.
    http://dx.doi.org/10.1109/MDT.2007.151

  112. R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, and A. Ivanov, ``System-on-Chip: Reuse and Integration'',
    Proceedings of IEEE, 94(6), June 2006, pp. 1050-1069.
    http://dx.doi.org/10.1109/JPROC.2006.873611



    Peer-to-Peer Storage Systems

  113. A. Javidan, T. Angerilli, G. Lemieux, R. Lisagor, M. Ripeanu, ``An Exploration in Peer-to-peer Collaborative Back-up Storage'',
    IEEE Canadian Conference on ECE, Vancouver, BC, pp. 219-222, April 2007.
    presentation unavailable



    DC/DC Power Conversion

  114. S. Sheikhaei, M. Alimadadi, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer,
    ``Energy Recycling from Multigigahzertz Clocks using Fully Integrated Switching Converters'',
    IEEE Transactions on Power Electronics, 28(9), September 2013, pp. 4227-4239.
    http://dx.doi.org/ 10.1109/TPEL.2012.2237041

  115. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, P. Palmer, W. Dunford,
    ``A 4GHz Non-resonant Clock Driver with Inductor-assisted Energy Return to Power Grid'',
    IEEE Transactions on Circuits and Systems I, 57(8), August 2010, pp. 2099-2108.
    http://dx.doi.org/10.1109/TCSI.2009.2037850

  116. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, P. Palmer, W. Dunford,
    ``A Fully Integrated 660 MHz Low-swing Energy-recycling DC-DC Converter'',
    IEEE Transactions on Power Electronics, 24(6), June 2009, pp. 1475-1485.
    http://dx.doi.org/10.1109/TPEL.2009.2013624

  117. M. Alimadadi, ``Recycling Clock Network Energy in High-performance Digital Designs using On-chip DC-DC Converters'',
    Ph.D. Thesis, Department of Electrical and Computer Engineering, University of British Columbia, July 2008.
    presentation not available

  118. M. Alimadadi, S. Sheikhaei, G. Lemieux, P. Palmer, S. Mirabbasi, W. Dunford, ``A 660MHZ ZVS DC-DC Covnerter Using Gate-driver Charge-recycling in 0.18um CMOS with an Integrated Output Filter'',
    IEEE Power Electronics Specialists Conference, Rhodes, Greece, June 2008, pp. 140-146.
    presentation

  119. G. Lemieux, M. Alimadadi, S. Sheikhaei, P. Palmer, S. Mirabbasi, ``SoC Energy Savings = Reduce+Reuse+Recycle: A Case Study Using a 660MHz DC-DC Converter with Integrated Output Filter'',
    IEEE Canadian Conference on ECE, Niagara Falls, ON, pp. 947-950, May 2008.
    presentation

  120. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. Dunford, P. Palmer, ``Energy Recovery from High-frequency Clocks using DC-DC Converters'',
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, pp. 162-167, April 2008.
    presentation

  121. M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, P. Palmer, ``A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter'',
    IEEE International Solid State Circuits Conference, San Francisco, pp. 532-533, February 2007.
    presentation
    press release: ISSCC 2007 Press Kit
    press coverage: EDN: ISSCC 2007 Preview
    press coverage: EETimes Japan Feature Article (Google translation)



    Multiprocessors

  122. G. Lemieux, S. Caranci, R. Grindley, and K. Loveless ``NUMAchine Global Ring Hardware Design'',
    Technical Report, Department of Electrical and Computer Engineering, University of Toronto, March 2001. 49 pages plus missing schematics.

  123. R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic
    ``The NUMAchine Multiprocessor'',
    International Conference on Parallel Processing, Toronto, Canada, pp. 487-496, August 21-24, 2000.
    presentation

  124. A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic
    ``Design and Implementation of the NUMAchine Multiprocessor''    ,
    Proceedings of the 35th IEEE Design Automation Conference, San Francisco, CA, June 1998.

  125. S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, Z. Zilic,
    NUMAchine Hardware Reference and Maintenance Manual,
    Department of Electrical and Computer Engineering, University of Toronto, June 1998. 126 pages.

  126. S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, Z. Zilic,
    NUMAchine Principles of Operation for System Programmers,
    Department of Electrical and Computer Engineering, University of Toronto, June 1998. 60 pages.

  127. G. Lemieux, ``Hardware Performance Monitoring in Multiprocessors'',
    M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, June 1996.
    (other options)

  128. Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. Elkateeb, and S. Srbljic,
    ``The NUMAchine Multiprocessor'',
    CSRI Technical Report CSRI-324 (other options), Computer Systems Research Institute, University of Toronto, June 1995.

  129. T. Abdelrahman, S. Brown, T. Mowry, K. Sevcik, M. Stumm, Z. Vranesic, S. Zhou, A. Elkateeb, M. Gusat, P. Pereira, B. Gamsa, R. Grindley, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, G. Ravindran, S. Srbljic, Z. Zilic,
    ``An Overview of the NUMAchine Multiprocessor Project''    ,
    Proceedings of the 8th Canadian Supercomputing Conference, June 1994.