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- # of words per chip
- (no subject)
- [Asg 5: number of CS signals]
- A question
- A question about the assignment
- about the ass5 timing requirement
- address decoder
- Address range of the RAM system in Q.1?
- Asg 3
- Asg5
- ASS #1
- Ass#1
- ASS5
- assignemnt 5
- Assignment #3
- assignment #3 part 1
- Assignment #5: what does the clock have to do with it?
- Assignment 1 due time
- Assignment 3-- Stack Register
- Assignment 5
- Assignment 5 Solutions
- Assignment3
- Assignment3 : 3 ways to design ROM
- assignment5 question1
- buffer
- cpu_package file
- data transfer in serial interface
- Defining enumerated types in MaxPlus II
- Duplicate Instructions?
- EE 379 participation markss
- error message
- final
- Final Questions
- FPGAs
- help
- I still get the bus contention.
- in lab4, I have bus content.
- in lab4, I have bus content[ion]
- Lab
- Lab #3 counter question
- LAB 4
- Lab 4 Report
- lab03 - compile package file
- Lab4
- lab4 [now available]
- lab4: what is the idle signal?
- Lab5
- Marking of assignment 2
- Marks Breakdown for Assignment 1&2
- Memory design
- Midterm
- midterm (to Dr Casas)
- Midterm weight
- Office Hours
- old labs and assigments
- Open-collector
- PCI bus
- Please check your EECE 379 mark
- possible change to course marking scheme
- Question about serial interface
- question about the lab marks
- Questions about system bus
- Reserving Memory
- room change?
- SBC/FPGA
- Serial Device Interface
- status port
- T or F questions
- Testing
- the IN instruction
- The ROM
- timing stuff
- To Prof. Casas
- Vague Specs
- VHDL 1987 or VHDL 1993?
- Welcome to EECE 379
- your mail
- your mail [memory decoder]
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