Re: timing stuff

Ed Casas (edc@ece.ubc.ca) Thu, 13 Apr 2000 16:54:25 -0700 

Date: Thu, 13 Apr 2000 16:54:25 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: timing stuff



On Thu, Apr 13, 2000 at 02:32:45PM -0700, ddowler wrote:
> i am attemting the exam from january 99 right now.  how do you expect us
> to handle a case like tDW (data hold from write)?  tDW is a requirement
> of the ram chip, and the guaranteed response of the cpu chip shows that
> the data becomes invalid BEFORE the write strobe goes high, hence giving
> a negative guaranteed response (which we also have no value for).

Do you mean tDH?  If so, note that the RAM's write cycle ends
when either CS* or WR* goes high.  In this particular design the
write cycle is termined by CS* going inactive and the value of
tDW is tSNDOI (15 ns minimum) giving a margin of 15 ns.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592