Re: [Asg 5: number of CS signals]

Ed Casas (edc@ece.ubc.ca) Tue, 28 Mar 2000 07:07:19 -0800 

Date: Tue, 28 Mar 2000 07:07:19 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: [Asg 5: number of CS signals]



On Tue, Mar 28, 2000 at 03:42:13AM -0800, pwplau wrote:

> if a SRAM chip has 2 word/byte

The SRAM chips are 64k x 8.  The CPU bus width is 16 bits.

> it would need 12 chips for the 386SX CPU.  Then, the design
> would consist of 6 banks.

I don't follow this reasoning.

> How could that be possible that CS is only one bit (according
> to the description of the assignemtn, CS is either active high
> or low)??

Each chip has only one chip-select input (CS), but your decoder
has to generate several different chip select signals
(e.g. CS0H*, CS0L*, CS1H*, etc).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592