ddowler (ddowler@direct.ca) Thu, 13 Apr 2000 14:32:45 -0700
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Date: Thu, 13 Apr 2000 14:32:45 -0700 From: ddowler <ddowler@direct.ca> Subject: timing stuffi am attemting the exam from january 99 right now. how do you expect us to handle a case like tDW (data hold from write)? tDW is a requirement of the ram chip, and the guaranteed response of the cpu chip shows that the data becomes invalid BEFORE the write strobe goes high, hence giving a negative guaranteed response (which we also have no value for). thanks, dustin dowler eece 379
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