Re: Assignment3 : 3 ways to design ROM

Ed Casas (edc@ece.ubc.ca) Sun, 5 Mar 2000 06:21:56 -0800 

Date: Sun, 5 Mar 2000 06:21:56 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Assignment3 : 3 ways to design ROM



On Sat, Mar 04, 2000 at 09:34:24PM -0800, Jun Wang wrote:
> I got 3 version of ROM  design
> 1. using conditional statement
>                data <=    instruction   when address =  xx
> 2. using with and select statement which is similar to the first design.
> 3. using array element in MaxplusII  for example
>          type byte_array  is array of (0 to 31)  ;
>          signal      ROM : byte_array;
>          ROM(i) <= instruction .....
>          data <= ROM(address);
> It seems to me the first 2 designs has more glitches in output than the 3rd 
> design and I guess that's because the structure created by first 2 design is 
> complicated.
> Unlike using the array which is specificly for the ROM or RAM is simple and 
> efficient in structure. 

Any of these is acceptable.  The synthesizer is actually free to
choose any implementation that will meet your time/space
requirements but the structure of the first version implies a
multiplexer tree while the second and third options imply a
ROM-like structure that maps input to output with a fixed number
of levels of logic.

> However, there's a problem in using ROM. As we only use 32-byte
> ROM but the address is 8 bit long which would allocate a
> 256-byte ROM. Of course, we can ignore MS 3 bit in input address
> and can access the ROM contents by index, but u will recieve a
> warning of the input pins are ignored etc. u can use these
> 3-bit to do some dummy job to avoid the warning but that seems
> unreasonable to me and also I find the3rd design takes long
> time to comple. So I wonder what is the best design that fits
> our needs.

You can not ignore the MS 3 bits of the address because the
assignment says that unused ROM locations have to be set to zero.

You should try to keep your design as portable as possible so you
don't lock yourself into one vendor or technology.  However,
memories are one place where it's often necessary to make your
design vendor-specific since the gains in speed and size can be
very large.

Many FPGAs (including the Altera ones you are using for these
assignments) have special logic blocks that can be used to
implement memory blocks efficiently.  You can make use of these
by instantiating vendor-specific components but then your design
will not be portable to other device manufacturers.  A better way
is to give the synthesizer hints that a particular function
should be implemented with a certain type of block (typically
using ``attributes'').

For this assignment you won't need to do this.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592