Re: address decoder

Ed Casas (edc@ece.ubc.ca) Tue, 28 Mar 2000 07:20:17 -0800 

Date: Tue, 28 Mar 2000 07:20:17 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: address decoder



On Tue, Mar 28, 2000 at 11:25:33AM +0000, Carmen Lee wrote:

> How are we going to write the VHDL code for OE???
> 
> Does that depend on the address bus???

It wouldn't hurt if you designed the circuit so that the
different OE* signals are only asserted when the corresponding
CS* signal is active. But, as explained in the the lecture notes,
the tri-state outputs will not be enabled unless CS* is also
asserted.  So OE* can be the same signal for all of the chips.

> If that is the case, would OE be asserted if one of the IC
> required address bus is asserted?  For example, what if each IC
> requires N=16 address bus?

I'm afraid I don't understand the question.  Each IC does require
16 bits of address (there are 64k locations per chip) but the
control of OE* is unrelated to the number of address bits
required by the chip.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592