I still get the bus contention.

Xin Sun (sun.simon@usa.net) Tue, 29 Feb 2000 18:54:06 -0800 

From: "Xin Sun" <sun.simon@usa.net>
Subject: I still get the bus contention.
Date: Tue, 29 Feb 2000 18:54:06 -0800




Hi, everyone,
I still get the bus contention. I don't know why?
The problem doesn't occur during the enable signal='0'. It only
occurs at signal enable='1'. I think it is reasonable, because
signal='1', I will drive the data to the data_bus, but at that time
who can guarantee I can use the data bus. I think only the ior
signal. Before signal ior* is asserted, the computer should grant
the data bus to the FPGA. The problem is that I can't change
the value of data_bus to "zz" at that time when enable='1'.
It's wired.