FPGAs

Simon Tang (simon-tang@home.com) Thu, 13 Apr 2000 17:27:23 -0700 

From: "Simon Tang" <simon-tang@home.com>
Subject: FPGAs
Date: Thu, 13 Apr 2000 17:27:23 -0700



A question not relating to the final, but something that I've wanted to know
for a while, is how do you gauge the "fullness" of an FPGA.  During the
course, it seemed that we took it for granted that we had unlimited
resources (granted, that the circuits we designed were relatively simple).
During the design process or when you compile your design, how can you
determine the number of gates used in the design?

Simon Tang