Re: in lab4, I have bus content[ion]

Ed Casas (edc@ece.ubc.ca) Tue, 29 Feb 2000 14:43:11 -0800 

Date: Tue, 29 Feb 2000 14:43:11 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: in lab4, I have bus content[ion]



On Sun, Apr 06, 2036 at 08:25:10PM -0800, SIMON SUN wrote:

> I have a question about the lab4.  When I simulate the VHDL, I
> get bus content.

I think you mean "bus contention."  This is the term for two
devices driving a bus at the same time (a no-no).

> When I ior*=0, and address=220h, and idle status, and
> ext_load=0. The data_bus ="00000001".  I got the result which
> is "0x".  I don't know why.  Thanks for help Xin

The contention is probably caused by the *simulator* driving the
data bus at the same time that your tri-state buffer output is
enabled.

Set the value you are driving on the data bus during reads to
"ZZ" (high impedance) and this should fix the problem.

And...

			 ***************
			 * PLEASE NOTE *
			 ***************

I've placed a description of how to check your design's maximum
clock rate to the course web page.  Please check your design's
timing before going into the lab in order to avoid nasty
surprises.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592