Re: A question

csimpson@ieee.org Wed, 12 Apr 2000 02:37:47 -0600 

From: csimpson@ieee.org
Date: Wed, 12 Apr 2000 02:37:47 -0600
Subject: Re: A question



At 03:00 PM 4/11/00 PDT, you wrote:
>What's the difference between an edge triggered signal and a level 
>(sensitive)triggered one?
>
>May Siksik
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>

Edge triggering implies that a process occurs when a trigger signal
transitions from one state to another (generally low to high, or 'positive
edge triggering'). An example might be the capture of data from a data bus
into a register when an associated data clock signal goes from low to high.

Level sensetive latches are a little different - the output of the latch
will match it's input, so long as the enable ('trigger') signal indicates
that the latch should be active. That is, if the enable signal indicates
'on', then the latch will be trasparent... the latch output would follow
the input after only a gate propogation delay. When 'enable' changes to the
'off' state, the latch output will be frozen in the last state the input
was at when the enable signal was 'on'.

To illustrate my point, here's a crude timing diagram for a 4-bit register
(should be viewed with a fixed width font):

'trigger' signal:   1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0
input data:         0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4
edge triggered
register value:     X X X X X 5 5 5 5 5 5 5 5 5 E E E E E E E
level sensetive
register value:     0 0 0 0 0 5 6 7 8 9 A A A A E F F F F F F

Note that the term 'edge triggered' can be used to describe any type of
circuit or process which is triggered by a signal 'edge', whereas I have
only ever heard the term 'level sensetive' used to describe this particular
type of latch.

hope that helps,

Chad Simpson
___________________________________
Electrical Engineering Team Leader,
Formula UBC
csimpson@ieee.org