Re: FPGAs

Ed Casas (edc@ece.ubc.ca) Thu, 13 Apr 2000 23:10:27 -0700 

Date: Thu, 13 Apr 2000 23:10:27 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: FPGAs



On Thu, Apr 13, 2000 at 05:27:23PM -0700, Simon Tang wrote:
> A question not relating to the final, but something that I've wanted to know
> for a while, is how do you gauge the "fullness" of an FPGA.  During the
> course, it seemed that we took it for granted that we had unlimited
> resources (granted, that the circuits we designed were relatively simple).
> During the design process or when you compile your design, how can you
> determine the number of gates used in the design?

As Craig mentioned, the synthesizer will tell you.  It generates
a report file with a very detailed description of the synthesis
results.

It is usually not possible to use 100% of the chip's logic blocks
because there may not be enough routing resources (essentially,
bus lines) to interconnect them.  Typically, you'll be doing well
if you end up with a design that is able to use 90% of the logic
blocks.

Logic synthesizer have sophisticated optimization algorithms that
try to squeeze your design into the available resources and also
try to make it run as fast as possible. But eventually (on most
projects) your design will get too large (or too slow).  Then
you'll get an error message saying that your design could not be
fit into the chip.  Then you have to simplify your design or go
to a larger (or faster) chip.

Different manufacturers use different types of logic blocks and
routing structures so it's not possible to compare different
manufacturer's chips based on the number of "equivalent gates"
they claim.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592