pwplau (pwplau@ece.ubc.ca) Tue, 28 Mar 2000 03:42:13 -0800
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
- New Message to:eece379@listhost.ece.ubc.ca
- Reply to:(no subject)
- Next message: Ed Casas: "Re: [Asg 5: number of CS signals]"
- Previous message: Carmen Lee: "address decoder"
- Next in thread: Ed Casas: "Re: [Asg 5: number of CS signals]"
- Reply: Ed Casas: "Re: [Asg 5: number of CS signals]"
Date: Tue, 28 Mar 2000 03:42:13 -0800 From: pwplau <pwplau@ece.ubc.ca> Subject: Re:if a SRAM chip has 2 word/byte, it would need 12 chips for the 386SX CPU. Then, the design would consist on 6 banks. How could that be possible that CS is only one bit (according to the description of the assignemtn, CS is either active high or low)??
- Next message: Ed Casas: "Re: [Asg 5: number of CS signals]"
- Previous message: Carmen Lee: "address decoder"
- Next in thread: Ed Casas: "Re: [Asg 5: number of CS signals]"
- Reply: Ed Casas: "Re: [Asg 5: number of CS signals]"