Re: status port

Ed Casas (edc@ece.ubc.ca) Thu, 2 Mar 2000 08:18:12 -0800 

Date: Thu, 2 Mar 2000 08:18:12 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: status port



On Thu, Mar 02, 2000 at 01:25:52AM -0800, Eric Wei wrote:
> Hi,

> Can anyone tell me how and where does the status port fit into
> the big picture?

The status port is an input port just like the one you
implemented in the previous lab.  It gives you information
about the state of the serial port.   Specifically it tells you
when it's "safe" to write a new value to the output (data) port.

> More specificaly, when is the status port generating data
> output when the entire circuit is taking data in on the same
> bus? So this circuit is actually generating data that gets fed
> back into itself?

The two things don't happen at the same time.  The CPU ensures
that IOR* and IOW* are never asserted at the same time.

So, although the data port's input mux is connected to the same
data bus as the status port's tri-state buffers, the contents of
data port won't be affected unless the CPU is doing a write (in
which case the tri-state buffers are disabled).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592