Re: Assignment #5: what does the clock have to do with it?

Ed Casas (edc@ece.ubc.ca) Wed, 29 Mar 2000 20:44:32 -0800 

Date: Wed, 29 Mar 2000 20:44:32 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Assignment #5:  what does the clock have to do with it?



On Wed, Mar 29, 2000 at 06:14:48PM -0800, Andrew Ching Hong Yung wrote:
> I know this is a little late, but here goes:
> 
> Do we even need to consider the clock (tCK = 33 ns)?  None of the timing
> diagrams seem to explicitly include it, and we know we can already assume
> that there are no wait states or address holds or bus idle cycles
> (W=DT=HI=0).

I included the clock period to explain why DT=0, you won't need
to use the clock period explicitly.

> I'm actually a little bit confused about why we need to include
> tCK into any timing diagram (like the example on page 7 in the
> timing analysis notes).

CPU specifications are often given as a function of the clock
period.  In this assignment that's not the case since W=DT=0.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592