Re: Testing

Ed Casas (edc@ece.ubc.ca) Sun, 27 Feb 2000 19:56:03 -0800 

Date: Sun, 27 Feb 2000 19:56:03 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Testing



On Sun, Feb 27, 2000 at 06:58:30PM -0800, ddowler wrote:

> Do we really need to hand in tests of our design?

VHDL descriptions seldom work the first time (at least, mine
don't) and usually require debugging.  There will probably be a
few "loose ends" that you won't catch until you actually try to
make it work.

So yes, you must simulate and submit the simulation results to
show that your designs work.

> I think it is pretty obvious what the output of the ROM will be
> just from looking at the code, and the stack register code is
> very short and sweet as well.  If we do need to hand some tests
> in, can you tell us exactly how we should test the components?

The list at the bottom of page 2 tells you what you have to test
(as a minimum):

- to test the ROM feed it all the relevant inputs (the assignment
tells you what these are) and show the outputs.

- to test the stack, set the inputs so that the stack does a
push, then a pop and then a hold and verify that the outputs are
what you expected.  You'll have to use some judgment in your
choice of inputs so the outputs actually demonstrate correct
behaviour (e.g. the data output should actually change with each
operation).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592