Ed Casas (edc@ece.ubc.ca) Wed, 1 Mar 2000 07:04:19 -0800
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Date: Wed, 1 Mar 2000 07:04:19 -0800 From: Ed Casas <edc@ece.ubc.ca> Subject: Re: I still get the bus contention.On Tue, Feb 29, 2000 at 06:54:06PM -0800, Xin Sun wrote: > ... The problem is that I can't change the value of data_bus to > "zz" at that time when enable='1'. There are two data bus signals in the waveform editor: the FPGA input and the FGPA output. Overwrite the FPGA input with a "group" value of "ZZ." -- Ed Casas edc@ece.ubc.ca http://casas.ece.ubc.ca +1 604 822-2592
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