LAB 4

ddowler (ddowler@direct.ca) Wed, 01 Mar 2000 16:13:21 -0800

• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
• New Message to:eece379@listhost.ece.ubc.ca
• Reply to:LAB 4
• Next message: Ed Casas: "Re: LAB 4"
• Previous message: Ed Casas: "Re: I still get the bus contention."
• Next in thread: Ed Casas: "Re: LAB 4"
• Reply: Ed Casas: "Re: LAB 4"

---

Date: Wed, 01 Mar 2000 16:13:21 -0800
From: ddowler <ddowler@direct.ca>
Subject: LAB 4


in the lab handout on page 2, the block diagram for "clock generator and
controller" shows that state (and various other signal groups) is 4 bits
wide.  why is this?  dont we only need 2 bits to encode the state?

---

• Next message: Ed Casas: "Re: LAB 4"
• Previous message: Ed Casas: "Re: I still get the bus contention."
• Next in thread: Ed Casas: "Re: LAB 4"
• Reply: Ed Casas: "Re: LAB 4"