Assignment #5: what does the clock have to do with it?

Andrew Ching Hong Yung (ayung@physics.ubc.ca) Wed, 29 Mar 2000 18:14:48 -0800 (PST) 

Date: Wed, 29 Mar 2000 18:14:48 -0800 (PST)
From: Andrew Ching Hong Yung <ayung@physics.ubc.ca>
Subject: Assignment #5:  what does the clock have to do with it?



I know this is a little late, but here goes:

Do we even need to consider the clock (tCK = 33 ns)?  None of the timing
diagrams seem to explicitly include it, and we know we can already assume
that there are no wait states or address holds or bus idle cycles
(W=DT=HI=0).

I'm actually a little bit confused about why we need to include tCK into
any timing diagram (like the example on page 7 in the timing analysis
notes).

Thanks!

-ANdrew