ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• ELEX 2117 Course Information
• marking
• Coding Guidelines
• Report and Video Guidelines
• Software Installation and Use
• Common Lab Errors
• indent
• draw.io diagram editor
• ELEX 2117 Report Example (MS Word)
• ELEX 2117 Report Template (MS Word)
• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL
• Lecture 2 - State Machines
• Lecture 3 - Examples of State Machines
• Lecture 4 - Simulation
• Lecture 5 - Interfaces
• Lecture 6 - Timing Analysis
• Lecture 7 - Implementation of Digital Logic Circuits
• Lecture 8 - Analog Interfaces
• Lecture 9 - Hierarchical Design
• Lecture 10 - Implementation Technologies
• Lecture 11 - HDL Idioms
• Summary of Learning Objectives
• Exercises and Answers
• lec1-exercises
• lec1-exercises_annotated
• lec2-exercises
• lec2-exercises_annotated
• lec3-exercises
• lec3-exercises_annotated
• lec4-exercises
• lec4-exercises_annotated
• lec5-exercises
• lec5-exercises_annotated
• lec6-exercises
• lec6-exercises_annotated
• lec7-exercises
• lec7-exercises_annotated
• lec8-exercises
• lec8-exercises_annotated
• lec9-exercises
• lec9-exercises_annotated
• lec10-exercises
• lec10-exercises_annotated
• lec11-exercises
• lec11-exercises_annotated
• Labs
• Lab 0 - Practice Lab

  Version 2: Corrected clock input pin number in CPLD description.  The pin number (12) in the procedure section is correct.

• Lab 1
• Lab 1 - Combinational Logic Design with Verilog
• lab1demo.mp4
• lab1.pof
• Lab 2
• Lab 2 - Sequential Logic Design with Verilog
• clkdiv.sv
• lab2_1Hz
• lab2_5kHz
• lab2demo.mp4
• Lab 3
• Lab 3 - Timers and Clock Dividers
• lab3demo.mp4
• lab3.qsf
• lab3.pof
• Lab 4
• Lab 4 - Matrix Keypad Decoder

  Revision 1: Corrected labelling of state machine in block diagram.

• lab4.qar
• lab4demo.mp4
• lab4.pof
• Lab 5
• Lab 5 - Simulation

  Revision 1: Corrected initial test vector.

  Revision 2: Corrected example simulation output.

• Lab 6
• Lab 6 - Logic Level Conversion
• Lab 7
• Lab 7 - SPI Interface
• lab7.qar
• lab7_tb.sv
• lab7tv.csv
• lab7demo.mp4
• lab7.pof
• Lab 8
• Lab 8 - Sigma‑Delta ADC
• lab8demo.mp4
• lab8.sv
• lab8modules.sv
• lab8pins.qsf

  You can import this file to assign the pins as shown in the lab notes.

• Quizzes and Exams
• Quiz 1
• Solutions to Quiz 1
• Midterm 1
• Solutions to Midterm 1
• Quiz 2
• Solutions to Quiz 2
• Midterm 2
• Solutions to Midterm 2
• Quiz 3
• Solutions to Quiz 3
• Final Exam
• Solutions to Final Exam
• Datasheets

  These may or may not be the datasheets for the components we will be using.

• EPM240-Minimal-Development-Board-Schematic
• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Student Evaluations