Marking Scheme

Labs

Note: For any solution to be considered correct the course coding guidelines must be followed. No marks awarded otherwise (e.g. use of if/else, begin/end or case statements). 

                              Lab 0: (12)

Report formatting (2)
  - has cover page with (1) course name & number, (2) lab number &
    title; (3) student name & number; (4) date (-1 per missing item)

Screen capture (1)
  - includes readable compilation report details
  - shows more than compilation report (e.g. complete screen) (-1)
  - not taken with a screen capture utility (e.g a phone) (-1)
  
Code Listing (3)
  - includes required file-level comments
  - monospaced font with single spacing
  - indentation matches code structure and indentation levels are consistent
  - text, not an image (-1)

Block diagram (3)
  - legible, upright
  - drawn by student, not Quartus RTL Netlist Viewer
  - matches diagram in Report and Video guidelines in all respects
    (symbols, port labels, bus widths, expressions)

Submitted video file (3)
  - shows the blinking LED
  - properly oriented
  - less than 25 MBytes and plays in browser
  - a file, not a link (-3)


                              Lab 1 (10)

- cover page (1)
- block diagram matching code (1)
- listing matching demo (1)
- compilation listing matching your code (1)
- demo (video or in lab) (6)

- marks deducted for any report and video guidelines not followed
- no marks if video is too large or not viewable in browser


                              Lab 2 (10)

- report has correct cover page (1)
- listing conforming to coding guidelines (2)
  - file-level comments -1
  - consistent indentation -1
  - use of always_ff with single non-blocking assignment -1
- block diagram matching the Verilog and conforming to report
  guidelines (not from Quartus) (1)
- correct digits displayed in the right position (2, -1 for each incorrect digit)
- correct digits displayed in the right order (2, -1 for each digit in wrong order)
- all digits displayed simultaneously with 5 kHz clock (1)
- correct orientation of digits on video (1)

 Comments:
1 block diagram does not conform to guidelines or your code: -1
2 wrong digits displayed: -2
3 digits displayed in wrong order: -2
4 no photo of display with 5kHz clock: -1
5 violation of coding guidelines: -2
6 incorrect orientation of digits in video: -1
7 incomplete file-level comments: -1
8 inconsistent indentation: -1


                              Lab 3 (10)

- both demos completed during the lab: 10

                              Lab 4 (10)

- block diagram matching the student's keypad.sv conforming to report
  guidelines (1)
  - one multiplexer per conditional operator
  - one register per always_ff statement
  (not generated by Quartus, not the one from the lab instructions,
  not using arbitrary symbols)
- Verilog listing with (2)
  - correct file-level comments
  - correct indentation
- screen capture of compilation report (1)
- demo or video showing effect of pressing each key (6)
  - -1 for each key displaying incorrect value (except * and #)
  - -3 for each incorrect display for * or #

 Comments:
1 Diagram does not conform to course coding guidelines: -1
2 Missing/incorrect file-level comments: -1
3 Missing/incorrect indentation: -1
4 Missing/incorrect compilation report: -1
6 Demo OK

                              Lab 5 (10)

- listing of DUT .sv file (1)
        - -0.5 per coding or report guidelines violation
        - -0.5 if input on reset is not loaded to a register
- listing of testbench .sv file (1)
        - -0.5 per coding or report guidelines violation
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (6):
  - reset asserted and sets output to zero
  - input value when reset asserted is equal to floor(mean of the student ID digits)
  - sequence of 8 input digits corresponds to the student's ID
  - count output value increases by 1 only for digits > mean
  - correct final count
  - correct error message on last test vector

                              Lab 6 (10)

- one mark per screen capture (4)
  - showing a 3.3V square wave on TP1
  - showing a 5V square wave on TP3
  - showing TP3 at 5 V and inverted relative to TP2
  - showing TP3 at 3.3 [inverted relative to TP2]
- what happens at TP1 when TP2 is grounded (1)
- power dissipation in pull-up resistor for 3.3V and 5V (1=2x0.5)
- demo during lab (4)

                              Lab 7 (10)

- correct calculation of the required output voltage and 8 (or 16-bit) value (2)
- listing of Verilog code for the spi module meeting course 
  requirements (indentation, correct use of always_ff 2)
- compilation report (1)
- screen capture of the RTL Netlist SPI module schematic (not the
  top-level lab6 schematic) (1)
- demo or video of zero output (1)
- demo or video of the correct voltage output (3)


                              Lab 8 (6)

- listing of Verilog code (indentation & file-level comments) (1)
- compilation report (1)
- RTL netlist diagram (from Quartus) (1)
- demo showing a range of at least from 500mV to 3 V (-1 if not full
  range shown, -2 if only shows ADC or only shows DMM) (3)

Quizzes


                             Quiz 1 (11)

Q1:

1 mark per correct answer (both width and value must be correct)

Q2:

1 mark for module/endmodule and name
1 mark for correct module declaration syntax
1 mark for correct assignment to output


                             Quiz 2 (18)

Q1(2):

1 mark per correct answer (both width and value must be correct)

Q2(2):

1 mark for correct equation/method
1 mark for correct answer

Q3(14):

- correct type and unique state encodings (2)
- reset into left state (1)
- correct outputs (5)
- correct transitions (6)


                             Quiz 3 (11)

Q1 (4)
 - formula x 2
 - answer x 2

Q2 (2)
 - formula
 - correct answer

Q3 (3)
 - signal power (2W or 4.5W)
 - SNR in dB and conversion to linear units (10^6.176)
 - correct noise power (1 or 3 uW)

Q4 (2)
 - answer
 - justification

Midterm Exams

    
                         Midterm Exam 1 (17)


Q1:
- one mark per correct answer (both width and value must be correct)

Q2:
- correct module declaration, including name and endmodule
- correct input and output declarations including dimensions
- correct add/subtract/hold (two correct conditional operators)
- correct register (always_ff)
- correct assignment to output

 Typical Comments:
1 incorrect module declaration: -1
2 missing/incorrect inputs or outputs: -1
3 missing/incorrect register: -1
4 missing/incorrect conditional operators(s): -1
5 incorrect output: -1

Q3:
- correct module declaration
- correct state variable declaration
- correct reset
- correct state transitions
- correct output

 Typical Comments:
1 incorrect module declaration: -1
2 missing/incorrect state variable: -1
3 missing/incorrect reset: -1
4 missing/incorrect state transitions: -1
5 missing/incorrect output: -1
7 incorrect state transitions (numeric literal syntax): -1


                         Midterm Exam 2 (17)

Q1:

- always_ff
- correct slice
- correct concatenation

Q2:

- correct waveform filled in
- correct bit order
- correct location of the bits
- correct bit values

Q3:

- always begin or initial begin ("at top level")
- wait or loop+if
- correct $display or $write
- correct $stop or $finish (after printing)

 Comments:
1 no always or initial: -1 
2 no wait (or loop+if): -1
3 no $stop or $finish: -1
4 syntax
5 wrong order: -1

Q4:

- find worst-case tPD
- solve for clock period
- correct clock period
- correct clock frequency

Q5:

- answer
- reasoning

 Comments:
1 see solutions: -2

Exam

                              Final Exam (41)
                              
Q1:

- module declaration
- always_ff
- correct reset mux
- correct enable mux
- correct outputs

 Typical Comments:
1 incorrect module declaration: -1
2 incorrect/missing reset: -1
3 incorrect count logic: -1
4 incorrect/missing outputs: -1
5 violates coding conventions: -1
6 incorrect always_ff: -1

Q2:

- one mark per correct answer (both width and value must be correct;
  9'h1040 was also accepted as correct for the second-last answer).

- according to the Verilog standard, bitwise-and (&) has higher
  precence then bitwise xor (^).  However, the lectures notes list
  them with the same precedence.  Thus either 32'h99 or 32'h1 were
  accepted as correct.

Q3:

- none are responses
- TWP is a pulse width
- setup times (tCLS, tCS, tALS, tDS)
- hold time (tALH, tDH)

 Typical Comments:
1 incomplete: -0.5
2 on the clock, not a setup or hold time: -0.5

Q4:

- one per noise margin (high: 0.3 or 0.27, low: 0.4)

Q5:

- one mark per correct answer (low: 0V, high: 10V or 20V)

Q6:

- +1 mark per correct value, -1 per incorrect (minimum 0, maximum 2)

Q7:

- correct pulse duration (0.1us or 0.2us)
- correct period (200us or 400us)

 Typical Comments:
1 wrong/missing pulse duration(width): -1
2 wrong/missing period: -1
3 units: -0.5
4 not exactly: -0.5
5 waveform inverted

Q8:

- one mark per correct answer

Q9:

- 1 for 3 labelled states
- 4 (1 for each correct transition, including reset)

Q10:

- declaration of clk and done
- DUT instantiation
- generation of clk signal (always, 0.125us for 4 MHz, 0.250us for 2 MHz)
- termination of simulation

 Typical Comments:
1 incorrect/missing declaration of clk and/or done: -1 
2 incorrect/missing instantiation of dut module: -1 
3 incorrect/missing generation of clk: -1 
4 incorrect/missing simulation termination: -1