You can download and use this spreadsheet to predict your final course mark. This spreadsheet assumes 8 labs.
Revision 1.
This corrects an error in the solution to Exercise 1.
This video demonstrates the required behaviour.
You can program you CPLD with this file to check if your hardware is working. It implements the required behaviour for a BCIT ID ending in 456.
Save this as lab7.sv, add your code to the spi module and change the value assigned to data
Pin assignments.
Test vectors.
If you used the pins suggested in the lab notes, you can program your CPLD with this file to check that your hardware is working properly.
Add your code to this file.
You can use these modules in your solution.
Pin, pull-up and drive strength assignments if you are using the same pin-outs
Add this file to your project if you want to be sure that your design will work with a 50 MHz clock.
Demonstration of a working design.
Note: download and install MAX II instead of Cyclone IV device support files.
Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).
These may or may not be the datasheets for the components we will be using.
Links to some additional [System] Verilog resources.