Marking Scheme

• Only the items below were checked.
• One mark was assigned for each item unless otherwise indicated.

Labs

                              Lab 0: (0)

                              Lab 1 (10)

- cover page (1)
- block diagram matching your code (1)
- listing matching your demo (1)
- compilation listing matching your code (1)
- demo (video or in lab) (6)

- half marks deducted if report and video guidelines not followed
- no marks if submission is the wrong format

                              Lab 2 (10)

- report has correct cover page (1)
- listing conforms to coding guidelines (2.5)
  - file-level comments -1
  - consistent indentation -1
  - use of always_ff with single non-blocking assignment -1
- report includes a plausible compilation report (0.5)
- correct digits displayed when 1 pressed (2, -1 for each incorrect digit)
- correct digits displayed when 4 pressed (2, -1 for each incorrect digit)
- any digits are displayed for pressing 1 and 2 but not for 7 or 5 (1)
- correct orientation of digits on video (1)

                              Lab 3 (10)

- Report with:
  - correct values of button, frequency and duration (0.5)
  - correct values of N and M (1)
  - block diagram (not from Quartus) (1)
  - Verilog code listing (1.5):
    - no file-level comments (-1)
    - correct indentation (consistent and 3-8 spaces) (-1)
- Demo of working circuit showing:
  - correct key pressed (2)
  - correct tone duration (2)
  - and correct frequency (2)

                              Lab 4 (10)

- a successful initial demo (3.5 marks)
- a successful demo of the requested change (2.5 marks)
- report (4 marks):
  - a listing of the initial design (only if successfully demonstrated in the lab)
  - a listing of the modified design (if successfully demonstrated in the lab)
  - proper file-level comments and indentation of the above code
  - a compilation report (of either design)

                              Lab 5 (10)

- listing of DUT .sv file (2, 1 if incorrect indentation or missing file-level comments)
        -0.5 for partial file-level comments
        -0.25 if no reset logic is implemented
        -0.5 for not following other course coding guidelines
- listing of testbench .sv file (2, 1 if incorrect indentation or missing file-level comments)
        -0.5 for partial file-level comments
        - 0.25 if detected output is printed instead of DUT internal state
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (4):
  - -2 if 1,2,3,4 sequence not used or triggers 'detected'
  - -2 if student ID test sequence does not trigger 'detected'
  - -4 if test sequence does not match student ID
  - -1 if missing test vector that has an error in the 'detected' result
  - -1 if missing test vector #3 (student ID with extra incorrect digit)


                              Lab 6 (10)

- one mark per screen captures (4)
- what happens at TP1 when TP2 is grounded (1)
- power dissipation in pull-up resistor for 3.3V and 5V (1=2x0.5)
- demo during lab (4)


                              Lab 7 (10)

- correct calculation of the required output voltage and 16-bit value (2)
- listing of Verilog code for the spi module meeting course
  requirements (comments and indentation, 2)
- compilation report (1)
- screen capture of the RTL Netlist SPI module schematic (not the
  top-level lab6 schematic) (1)
- demo or video of zero output (1)
- demo or video of the correct voltage output (3)


                              Lab 8 (6)

- listing of Verilog code (indentation & file-level comments) (1)
- compilation report (1)
- RTL netlist diagram (from Quartus) (1)
- demo showing a range of at least from 500mV to 3 V (-1 if not full
  range shown, -2 if only shows ADC or only shows DMM) (3)

Quizzes

                                Quiz 1 (11)

Q1(6): -1 per wrong answer (width, base and value must be correct)

Q2(2): -1 for wrong width, base or value

Q3(3): -1 for wrong declaration (name, inputs and outputs), -1 for no
or wrong assign statement, -1 for wrong expression in assign statement

                                Quiz 2 (11)

Q1(4):

  -1 per wrong answer (width, base and value must be correct)

Q2(4):
  - an always_ff statement assigning to st (2)
  - initial transition based on s AND state (1)
  - an assign statement assigning to o (2)
  - an assignment to o based on state (1)
  - correct values assigned to o (1)

                              Quiz 3 ()

Q1 (3)
- one mark per correct answer
Q2 (2)
- one mark per correct answer (must include units)
Q3 (5)
- one mark for each of:
  - module declaration
  - always_ff statement on clock
  - with reset on value == 0
  - with decrement based on value of fast
  - assign statement to out

Typical Comments:
1 incorrect module declaration: -1
2 error in always_ff: -1
3 no reset on count equal to zero: -1
4 incorrect decrement: -1
5 missing/incorrect assign to out(put): -1

                              Quiz 4 ()

Q1 1 mark per:

- initial block
- sets n to zero
- wait statement
- calls $stop
- always with #5us or #10us
- increments n by 1 or 2
- always with #20us or #40us
- $display() of n

Typical Comments:
1 syntax
2 incorrect initial: -1
3 does not initialize n: -1
4 incorrect stop condition: -1
5 incorrect stop: -1
6 incorrect always or delay: -1
7 incorrect increment of n: -1
8 incorrect display: -1

Q2 (6)
- correct bit values and bit order (2)
- correct data on MOSI vs MISO (2)
- correct SS framing (2)

Typical Comments:
1 incorrect bit order or values: -1
2 MOSI/MISO reversed: -2
3 SS* framing error: -2
4 data or SS* phase error: -1
5 clock rising edge should be in middle of bit period: -1
6 transition between levels should be much less than one clock period.


                              Quiz 5 ()

Exam