Version 2: Simplified rules for block diagrams.
Example video.
If you used the same pinouts as in the lab notes you can program your CPLD with this file to check that your hardware is working correctly.
You'll need to add this file to your project to generate a 200 Hz clock.
Program this file to test your hardware.
Demonstration video for Lab 2.
Rename to lab7.sv and fill in the missing code. Includes a testbench for simulation.
Settings file with pin assignments as in the lab notes.
Test vectors for simulation.
Revision 2 - screen capture 3 should include TP1 and TP3 (not TP1 and TP2 as previously stated in the Report section).
The rightmost (least significant) digit of your student ID determines which .pof file you should measure for Lab 9:
Rev.2: ledcnt width corrected to 16 bits; displays in video must be right-side-up.
Add your code to this file.
You can use these modules in your solution.
Pin, pull-up and drive strength assignments if you are using the same pin-outs as in the lab notes.
Add this file to your project if you want to be sure that your design will work with a 50 MHz clock.
Demonstration of a working design.
Note: download and install MAX II instead of Cyclone IV device support files.
Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).
These may or may not be the datasheets for the components we will be using.
Links to some additional [System] Verilog resources.