Marking Scheme

Labs

Note: For any solution to be considered correct the course coding guidelines must be followed. No marks awarded otherwise (e.g. use of sequential Verilog statements).

Lab 0


                                Lab 0

                             Lab 0: (0)

Report formatting (2)
  - has cover page with course name & number, lab number & title;
  - student name & number; date

Block diagram (5)
  - drawn by student, not RTL Netlist Viewer
  - legible
  - uses a multiplexer schematic symbol
  - signals and ports are labelled
  - bus widths (for a, b, y) are marked

Corrected code (5)
  - has comments at top with correct information (file name, purpose,
    author's name & date)
  - consistent indentation
  - changed wire and reg to logic
  - changed always to always_ff
  - single assignment in always_ff

Screen captures (1)
  - includes a compilation report
  
Submitted video file (3)
  - a file, not a link (-1)
  - video plays in browser (-1)
  - properly oriented (-1)

Lab 1


                                Lab 1

Cover Page (0.5)

  - has cover page with course name & number, lab number & title;
    student name & number; date (0.5)

Block Diagram (3)

  - signals labelled (1)
  - uses multiplexers with correct inputs (1)
  - correct literals in Verilog format (size, base & value) (1)

- Verilog listing (2)
  - file-level comments
  - reasonable and consistent indentation (3 to 8 spaces)

- compilation report (0.5)

- demo (video or in lab) (4)
  - correct orientation (1)
  - three correct numbers for keys (1, 2 and 3) as per ID (-2 per incorrect digit)
  - no display for other keys (A, 5, 9 and D) (-1)

                     Common Deductions for Lab 1

Cover page – incomplete: -0.5
Block diagram – incorrect: -2.0
Block diagram – signal labelling problems: -1.0
Block diagram – multiplexers with correct inputs: -1.0
Block diagram – literals in Verilog format (size, base, value) problems: -1.0
Verilog code – file level comments missing/incomplete: -1.0
Verilog code – indentation problem: -1.0
Compilation report missing: -0.5
Demo – incorrect orientation: -1.0
Demo – incorrect number: -2.0
Demo – no display for other keys: -1.0
Demo – display not on Rightmost digit: -0.5
Demo – display without pull-up Rs: -0.5
Demo missing: -4.0

Lab 2


Cover page (0.5)

Verilog listing (3)
  - uses always_ff (1)
  - file-level comments (1)
  - proper indentation (between 3 and 8 spaces) (1)

Compilation Report (0.5)

Demo (video or in lab) (4)
  - correct orientation (-1 if wrong)
  - if not blank when no key or key 3 pressed (-1)
  - all digits displayed and correct (max deduction -4)
    -0 if all correct
    -1 if one incorrect
    -2 if 2-7 incorrect
    -4 if all incorrect 

                          Common Deductions

Cover page – incomplete: -0.5
Block diagram – signal labelling problems: -1.0
Block diagram – multiplexers with correct inputs: -1.0
Block diagram – literals in Verilog format (size, base, value) problems: -1.0
Verilog code – file level comments missing/incomplete: -1.0
Verilog code – always_ff not used: -1.0
Verilog code – indentation problem: -1.0
Compilation report missing: -0.5
Demo – incorrect orientation: -1.0
Demo – 1 incorrect number: -1.0
Demo – more than 1 incorrect number: -2.0
Demo – all incorrect number: -4.0
Demo – display blanking – problem: -1.0
Demo missing: -4.0

Lab 3


                                Lab 3
Cover Page (0.5)

Verilog listing (4)
  - file level comments (0.5)
  - correct indentation (0.5)
  - uses always_ff (1)
  - scans from top row (0111) to bottom (1110) (1)
  - stops scanning when a button is pushed (1)

Compilation report (0.5)

Video/Demo (5)
  - subtract 1 mark for wrong display orientation in the video
  - subtract 1 mark for not testing letters (A-D)
  - subtract 2 per wrong digit
  - subtract 1 mark if * or # not right output

                          Common Deductions

Cover page missing: -0.5

Verilog code – file level comments missing/incomplete: -0.5
Verilog code – indentation problem: -0.5
Verilog code – always-ff not used: -1.0
Verilog code – scanning problem: -1.0
Verilog code – scanning while button pressed: -1.0
Verilog code – scanning problem – row 1110 to 0111: -1.0

Compilation report missing: -0.5

Demo – incorrect orientation: -1.0
Demo – A-D not tested: -1.0
Demo – incorrect numbers: -2.0
Demo – incorrect digit for */#: -1.0

No demo: -5.0

Lab 4 


                              Lab 4 (10)

Report (3)
  - cover page (0.5)
  - correct button, frequency and duration (1)
  - block diagram matching the submitted Verilog listing (hand drawn) (1)
  - block diagram (as produced by Quartus RTL netlist) (0.5)

Verilog code listing showing: (1)
    - file level heading (0.5)
    - correct indentation (consistent and 3-8 spaces) (0.5)

Compilation report (0.5)

Demo or video of working circuit (5.5)
- correct key causes a tone (0.5),
- correct tone duration independent of button press duration (1)
- correct tone duration (2), and
- correct frequency (2)

                     Typical Deductions/Comments

Report – cover page inadequate: -0.5 
Report – N, M incorrect (n1, n2, n3): -1.0
Report – hand drawn block diagram missing: -1.0
Report – hand drawn block diagram with problems: -0.5
Report – RTL block diagram missing: -0.5

Verilog code – file level comments missing/incomplete: -0.5
Verilog code – indentation problem: -0.5

Compilation report missing: -0.5

Demo – incorrect key (n1): -0.5
Demo – duration incorrect (when button pressed): -1.0
Demo – incorrect duration time (n3): -2.0
Demo – incorrect frequency: -2.0
Demo – missing: -5.5
Demo OK

N1 – 3rd ID digit from the right
N2 – 2nd ID digit from the right		f = 500 + n2*100 [Hz]
N3 – most right digit of ID		duration = 0.5 * (n3+1) [sec]

Lab 5 


- cover page (0.5)
- listing source code with file-level comments (1)
- consistent indentation (1)
- compilation report (0.5)
- RTL Netlist Schematic (1)
- demo (6)
  - reset clears (1)
  - correct sequence unlocks (3)
  - incorrect sequence doesn't (2)

Lab 6 


- listing of DUT .sv file (2, 1 if if correct indentation or missing  file-level comments)
- listing of testbench .sv file (2, 1 if incorrect indentation or  missing file-level comments)
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (4: same duration, different duration, early, late; -1 per mismatch)

Lab 7 


- correct calculation of the required output voltage and 16-bit value
  (1)
- listing of Verilog code for the spi module meeting course
  requirements (comments and indentation, 1)
- compilation report (1)
- screen capture of the RTL Netlist SPI module schematic (not the
  top-level lab6 schematic) (1)
- demo or video of the correct voltage output (5)

Lab 8 (10) 


- demo in lab (4)
- four screen captures (4=4x1)
- what happens at TP1 when TP2 is grounded (1)
- power dissipation in pull-up resistor for 3.3V and 5V (1=2x0.5)

Lab 9 (10) 


- table (subtract 1 for each mistake) (3)
- five screen captures (5)
- explanation of anomalous period measurement (1)
- calculation of rise time of scope (1)

Lab 10 (6) 


- listing of Verilog code (indentation & file-level comments) (1)
- compilation report (1)
- RTL netlist diagram (from Quartus) (1)
- demo showing a range of at least from 500mV to 3 V (-1 if not full
  range shown, -2 if only shows ADC or only shows DMM) (3)

Quizzes

Quiz 1


Q1

- module statement syntax and name
- inputs
- outputs
  
Q2

- correct width, base and value (-1 for each wrong)

Q3

- one mark per correct answer (all of width, base and value must be
  correct)

Q4

- labelled inputs and outputs
- correct component: a multiplexer or FF
- correct expression on select input or correct signal on clock
- correct expressions on the mux or data input(s)

Quiz 2

Quiz 3


Q1

- correct equations 
- correct results (2)

Q2

- correct type of function (AND or OR) and variables
- correct equation

Q3

- correct equation
- correct result

Exams

Midterm Exam 1


Q1 (4)

- one mark per correct answer (both width and value must be correct)

Q2 (2)

- correct period (100,000)
- correct starting value (99,999)

Q3 (4)

- r=1 transition to 00/11 (1)
- s=1 transition from 00/11/to 11 (1)
- t=1 transition from 01 to 10 (1)
- t=1 transition from 10 to 01 (1)

- under- or over-constrained transition conditions (e.g. based on a
  conditions not listed) or under(-1)

Q4 (5)

- correct number of states (3) and unambiguous labelling of the states
  (00/11, 10, 01) (1)

- correct transitions (4)

- under- or over-constrained transition conditions (e.g. not including
  !r when toggling between 01 and 10): -1

- although not strictly correct, not mark were deducted if a global
  reset was shown in the diagram and the !r condition was not included
  on any other transitions.

Q5 (7)

- module declaration (1)
- state register declaration (1)
- always_ff with clock and state as output (1)
- correct transitions (2)
- no state change if no conditions match (1)
- correct assign (1)

Midterm Exam 2



Q1

% module declaration
% logic array declarations of correct width (at least 5 and 4 bits)
% correct reset for both counters
% correct period for both counters (loads with 30 and 12 for periods of 31 and 13)
% correct output

Q2 (2)

% always and @(y) (or equivalent): 1 mark
% $display(x): 1 mark

Q3 (
% period (30ns)
% duty cycle (20ns high = 66%, 10ns high = 33%)

% correct equation
% correct result (100 MHz: 5ns; 10 MHz: 50ns)
% if you don't know your metric prefixes, bring a table


Q3 (2)

% always and @(y) (or equivalent): 1 mark
% $display(x): 1 mark

% active high: run, active low: run-bar: 1

Q5 (2) 

% clock input: requirement;
% propagation delay: guaranteed: 1
% measured to transition on input (output) (or similar): 1

Final Exam


                              Final Exam

Q1 (5)

- module declaration (1) 
- internal signal declaration (1)
- two conditional operators (1)
- four expressions (1)
- two registers (1)

Typical deductions/comments:

module declaration: -1
no s/d register: -1
expression error: -1
always_ff error: -1
error: -1
no answer: -5
syntax: -0.5
error: -0.5
OK: -0
☑️ OK


Q2 (8)

- one mark per correct answer

Q3 (3)

- -0.5 mark per incorrect value

Typical deductions/comments:

see solutions: -0.5
OK: -0
ambiguous: -0.5

Q4 (4)

- correct always_ff
- 6 state changes correctly conditioned on state
- 6 state changes correctly conditioned on input
- no change of state otherwise

Typical deductions/comments:

incorrect always_ff: -1
insufficient state change(s): -1
incorrect state change(s): -1
excessive state change(s): -1
state always changes: -1
error: -1
syntax: -0.5
violates course coding rules: -1
no answer: -4
☑️ OK: 0


Q5 (4)

- correct number of bits (8 in each direction, 16 total)
- correct MOSI value 
- correct MISO value
- correct values for each direction

Typical deductions/comments:

number of bits not given: -1
see solutions: -1
wrong direction: -1
direction not specified: -0.5
direction not specified: -1
no answer: -4
☑️ OK: 0


Q6 (2 )

- method
- answer

Typical deductions/comments:

see solutions: -1
☑️ OK: 0

Q7 (2)

- one mark per correct answer

Typical deductions/comments:

see solutions: -1
round up: -0.5
no answer: -2
☑️ OK: 0

Q8 (2)

- one mark per correct answer

Typical deductions/comments:

see solutions: -1
round up: -0.5
no answer: -2
☑️ OK: 0

Q9 (2)

- any attempt
- correct answer

see solutions: -1
no answer: -2
☑️ OK: 0


Q10 (1)

- 1 mark for a correct schematic
- -0.5 if included a pull-up

Typical deductions/comments:

see solutions: -1
open drain gate has no pull-up: -0.5
☑️ OK: 0

Q11 (5)

- 1 mark per correct answer

Typical deductions/comments:

see solutions: -1
☑️ OK: 0