ELEX 7660 - Digital Logic Design
Term 201810 (Winter 2018)
Announcements
Course Information
Course Information
Marking Scheme
Lectures
1 - Introduction to Digital Design with Verilog HDL
2 - State Machines
3 - System Verilog
4 - HDL Synthesis Idioms
5 - RTL Design
6 - Verification
8 - Static Timing Analysis
9 - Synopsis Design Constraints
10 -Timing Analysis
11 - Clock Domain Crossing
12 - Programmable Logic Applications and Architectures
Exercise Answers
lec1-exercises
lec2-exercises
lec3-exercises
lec4-exercises
Assignments
Assignment 1
Assignment 1 Question 1 Testbench
Assignment 1 Question 2 Testbench
Assignment 1 Question 3 Testbench
Solutions to Assignment 1
Assignment 2
Solutions to Assignment 2
Assignment 3
ADXL345
Solutions to Assignment 3
Exams
Midterm Exam - Part 1
Solutions to Midterm Exam 1
Midterm Exam - Part 2
Final Exam
Solutions to Final Exam
Resources
Interfacing
3V Tips ‘n Tricks
Project
Similar Project-Based Courses
Sources of Parts
Sources of IP
Project Guidelines
partsorder.xls
Verilog
Verilog Papers
Software
Software
Datasheets
FPGA (Cyclone 4) Datasheet
JST RE Series connectors
8-SEG-LED-Board-Schematic
4x4-Keypad-Schematic
Quadrature Encoder Rotation-Sensor-Schematic
Quadrature Encoder Rotation-Sensor-UserManual
0.95inch-RGB-OLED-Schematic
0.95inch-RGB-OLED-UserManual
SOLOMON SYSTECH SSD1331 96RGB x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller
TI ADC128S022 8-Channel, 50 kSPS to 200 kSPS, 12-Bit A/D Converter
PCB Mount Speaker 30mm 8 ohm 0.2W
74HCT244 Octal Buffer Datasheet
4N35 Optoisolator
Other
Including Code in Reports
Student Survey