The numbers in parentheses indicate the number of marked items (1
mark each).

			      Labs

Lab 1 Pre-Lab (2)

- 3 system Verilog modules
- 3 simulation output 

Lab 1 Report (3)

- working code (not including lab1.sv), 
- schematics 
- compilation summary

Lab 2 Pre-Lab (2)

- system Verilog code (3 modules)
- simulation transcript output 

Lab 2 Report (3)

- working code (3 modules + top level)
- the corresponding four schematics
- compilation summary

Lab 3 Pre-Lab (5)

- has >=2 registers (frequency and timer count)
- Verilog code for tonegen.sv.
- testbench output waveform
- C code for toneplayer.c.
- first 10 lines output

Lab 3 Report (3)

- Verilog and C code
- compilation summary
- Platform Designer schematic

Lab 4 Pre-Lab (4)

- listing for spimaster.sv
- testbench waveforms
- listing for lab4.c
- output of running lab4.c

Lab 4 Report (4)

- verilog code
- C code
- compilation report
- screen capture of system

Lab 5 Pre-Lab (2)

- code
- simulation results

Lab 5 Report (4)

- myfifo.sv listing
- compilation report
- console output
- signaltap output (with correct trigger value)


			   Assignments

Assignment 1 (6)

Q1

- computation using a case statement
- computation using initialized array

Q2

- uses a for-loop and bit indexing
- prints correct result from correct values

Q3

- has one alway_comb and one always_ff block
- correct simulation results

Assignment 2 (4)

- correct test value and sequence of bits
- reasonably complete testbench source code
- screen capture showing "passed" and correct value
- simulation waveforms

Assignment 3 (5)

- correct input and output pins
- correct timing analysis table (2)
- correct create_clock statement
- correct set_output_delay statement


			     Project

The project mark components are weighted as follows:

    % Component
   -- -----------
    3 Abstract
    5 Proposal
   10 Originality
   70 Accomplishment
   10 Report
    2 Demonstration

Parts List (out of 2) 

- required reformatting: 0
- some errors (e.g. URLs not hyperlinks): 1
- no errors: 2

[this was not included in the Project mark]

License (out of 1)

- submitted and correctly filled in: 1
- not submited: 0

[this was not included in the Project mark]

Abstract (7)

- includes names of team members (1)
- describes project motivation and objectives (2)
  - not at all (0), briefly (1), in some detail (2)
- additional material 
  - diagrams, tables &c as appropriate (1)
  - references (if not completely original) (1)
- standard of writing
  - does not contains errors (1)
  - has some obvious organization (1)

Proposal (5)

- introduction with motivation
- clear objectives
- enough diagrams to describe what will be build
- schedule with weekly milestones
- references (unless completely original)

The marking for the following four items are more subjective than
usual because the projects are so different.  Here are the
(approximate) guidelines I used when assigning the marks:

Originality (out of 5):

  highly original: 5
  some original aspects: 4
  not original: 3
  plagiarized: 0
  
Accomplishment (taking into account difficulty and completion) (out of 5):

  the expected amount of original work; succesfully completed: 5
  almost enough original work, successfully completed: 4
  less than the expected amount of work, or significant objectives incomplete: 3
  final design not working: 2
  no/little effort demonstrated: 0/1

Final Report (out of 5):

  clearly-written, error-free, complete: 5
  substantially complete: 4
  substantial omissions or other errors: 3
  minimal effort: 2
  nothing or almost nothing submitted: 0/1
    
Demonstration (out of 1):

  showed up, gave one: 1
  missed the demo: 0


			 Midterm Exam 1 (14)

Question 1

- 1/2 mark per correct answer
- 


			 Midterm Exam 2 (18)

Question 1

- module declaration with inputs and outputs
- multiply or subtract operation
- first mux
- first mux control
- second mux 
- second mux control (comparision or bit-select)
- register process
- register clock

Question 2

- labelled inputs and outputs
- address register
- w/ clock
- data register
- w/ clock
- address reset mux
- with correct inputs
- value reset mux
- with correct inputs

			   Final Exam

 Question 1 

- correct module declaration, inputs and outputs
- registering y (in always[_ff] @(posedge...))
- correctly nested if/else (or trinary operator)
- correct comparisons (max)
- an adder (+)


 Question 2 

- 4x 1-bit inputs and 1x 8-bit output
- 8-bit register clocked by clk
- mux controlled by reset and correct input value
- mux controlled by dup
- correct dup-false mux input value  (x and + or equivalent) 
- correct dup-true mux input value (repetition of nb value)

 Question 3 

- module and i/o declaration
- state register (must be edge-sensitive)
- A and B registers (@(posedge clk))
- correct next-state computation
- correct computation of next A, B values

 Question 4 

- module with correct inputs & outputs (*including* module)
- 3 registers (or 2 and 'done' set in comb logic)
- correct values on reset
- correct subtractions
- correctly set done on end condition

 Question  5

- correct equation
- correct fc and fd
- correct Ts (0.5 if used 20ns, 0 for 5ns)
- correct answer