ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• Course Information
• Lab Marking Scheme
• Software Installation and Use

  Revised January 31.

• Coding Guidelines
• Report and Video Guidelines

  Revised January 16.

• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL
• Lecture 2 - Flip-Flops and Registers
• Lecture 3 - System Verilog
• Lecture 4 - HDL Idioms
• Lecture 5 - Common Circuits

  Revised Feb 2.

• Lecture 6 - State Machines
• Lecture 6 - State Machines

  Revised Feb 23.

• Lecture 7 - Interfaces
• Lecture 8 - Timing Analysis
• Lecture 9 - Memory System Design
• Lecture 10 - Verification
• Lecture 11 - Implementation of Digital Logic Circuits
• Lecture 12 - Programmable Logic Applications and Architectures
• Summary of Learning Objectives
• Labs
• Lab 0 - Practice Lab
• Lab 1 - Combinational Logic Design with Verilog
• lab1demo.mp4
• lab1.pof

  Use this to test your circuit if you used the same pin assignments as in the lab notes.

• Lab 2 - Sequential Logic Design with Verilog
• lab2.mp4
• lab2.pof
• debounce.sv
• Lab 3 - Timers and Frequency Dividers
• lab3demo.mp4
• lab3.pof
• lab3.sdc
• Lab 4 -Multiplexed Display
• lab4.pof
• lab4.sdc
• Lab 5 - Modulo-n Counters

  Updated Feb 12.

• lab5demo.mp4

  Lab 5 demonstration video for n=7.

• lab5.qar
• lab5.pof
• Lab 6 - Quadrature Encoder Decoding
• lab6demo.mp4
• lab6.qar
• lab6.pof
• Lab 7 - Asynchronous Serial Interface
• lab7.qar
• lab7.pof
• Lab 8 - Simulation

  Revised Mar. 22.

• lab8_tb.sv
• lab8.sv
• Lab 9 - Digital Signal Measurements
• Exercise Answers
• lec1-exercises

  Updated Jan 19.

• lec2-exercises

  Updated Feb 3

• lec3-exercises
• lec3-exercises-incomplete
• lec4-exercises
• lec5-exercises

  Revised Feb 14.

• lec6-exercises
• lec7-exercises
• lec8-exercises
• lec9-exercises
• lec10-exercises
• lec11-exercises
• lec12-exercises
• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Other
• Parts Kits Contents
• Student Evaluations