Lab Marking Scheme

The items below were checked.  The marks assigned for each item are as
shown. Pn is the reference used in the Lab Comments on the Grades
page.

                              Lab 0: (0)

- submitted to correct folder and before labs collected (zero marks if not)

- report (R)
  - is a PDF file (R1)
  - has cover page with course name & number, lab number & name;
    student name & number; date (R2)
  - headings for each section (diagram, listing, compilation report)
    (R3)
  - includes a diagram (drawn by student) (R4)
  - diagram is readable and properly oriented (R5)
  - listing is text (R6)
  - listing uses a monospaced font (R7)
  - listing is single-spaced (R8)
  - diagram has caption (R9)

- diagram (D)
  - drawn by student, not RTL Netlist Viewer (D1)
  - legible (D2)
  - for schematics:
    - uses symbols similar to those used in lecture notes (D3)
    - signals and ports are labelled  (D4)
      - bus widths are marked if greater than 1  (D5)
  - for state transition diagrams:
    - state names and transition conditions labelled  (D6)

- code (C)
  - has comments at top with correct information (file nane, purpose,
    name & date) (C1)
  - same signal in every posedge of always_ff statement (C2)
  - no wire or reg signals (C3)
  - correct indentation (C4)
  - no always (only always_ff and always_comb) (C5)
  - only one x = x_next assignment in each always_ff (no multiple
    assignments or if/else/case) (C6)

  
- submitted video file (V)
  - a file, not a link (V1)
  - video plays in browser (V2)
  - video resolution not over 720p (V3)
  - properly oriented  (V4)
  
- submitted sample.sv file (F)
  - a text file, not PDF or .docx  (F1)

                              Lab 1 (8)

- PDF report (must be PDF, else mark for report is 0)
   P1: with cover page (1)
   P2: headings (1)
   P3: source listing properly formatted (1)
   P4: compilation report screen capture (1)

- Video (must be vieweable, else mark for video is 0)
   P5: correct digits displayed (4 or 2 if digits correct but not upright)


                              Lab 2 (6)

1. Cover page (0.5)

2. Verilog follows coding guidelines, specifically:

  (a) complete comments at beginning of the file (0.5)
  (b) declares and uses _next signal as input to register (1)

3. RTL diagram and compilation reports included (1)

4. correct video of student number (no marks if wrong number used)

   (a) numbers right-side up in video (1)
   (b) demonstrates reset (1)
   (c) demonstrates correct behaviour at end of number (1)


                           Lab 3 (8)

1. report with cover page and headings (0.5 + 0.5)

2. a block diagram of your design (1)

3. listing of the Verilog with (2)
	- file level comments (file name, date & name)
	- correct count value
	
4. scope scope capture (1 for any waveform, 2 for correct frequency)

5. video with three tones (1 mark for any tones, 2 for three tones)

                              Lab 4 (6)
					
1. calculation of clock divider from frequency (correct calculation and value) (1)
2. original block diagram (not from Quartus) (1)
3. Verilog source code (1)
4. photo of display (0 if wrong number, 1 if correct)
5. 'scope capture with correct frequency shown (1)
6. logic analyzer capture with correct digit enable sequence (1)

                              Lab 5 (6)

1. block diagram: 1
2. code listing: 1, -0.5 per violation of coding guidelines)
3. RTL netlist of modncount: 1 (-0.5 if shows the whole design)
4. video:
	(a) resets: 1
	(b) counts up and wraps at correct modulo value: 1 (-0.5 per deviation)
	(c) counts down and wraps at zero: 1 (-0.5 per deviation)

                              Lab 6 (7)

1. a block diagram (not from the Quartus RTL netlist viewer) of the
   qdecoder module showing clocks, register(s), multiplexers, and some
   decoding logic that generates up and down outputs (1)

2. a listing of the qdecoder.sv file with correct file-level comments and indentation (1)

3. screen capture of the compilation report with plausible values (1)

4. the RTL netlist viewer schematic (1)

5. video of the quadrature encoder decoder showing:
   - count increasing by at least 100 (1)
   - count decreasing back past zero (1)
   - count returning to original value when shaft returns to original angle (1)

                              Lab 7 (4)

1. Verilog listing of uart.sv (with correct indentation and file-level headers) (1)
2. UART schematic with state machine (-0.5 if no (yellow) state machine block) (1)
3. Logic analyzer screen capture with correct decoded student ID (2)

                              Lab 8 (6)

1. Verilog listing of uart.sv (with correct indentation and file-level headers) (1)
2. list of test vectors matching the student ID (1)
3. screen capture of waveforms showing at least x, y and the output (1)
4. transcript screen capture (3 if no errors, 2 if 1 error, 1 if 2 errors, 0 otherwise)


                              Lab 9 (10)

1. a PDF file with BCIT ID, name and date (3 items) (1 mark)

2. complete table of component values with at least 3 columns
   (reference designator, value and units) and 6 rows (R1, R2, R3, C1,
   C2, D1 forward voltage drop) and reasonable values (1 mark for a
   table, 2 marks if complete)

3. four screen captures (threshold, rise time, fall time,
   duty-cycle/period) (4 marks)

4. summary table with at least 5 columns (measurement type, graticule
   measurement, cursors measurement, "Measurement" measurement, units)
   and 7 rows (7 different measurements) (1 mark for table, 2 marks if
   complete)

5. photograph of circuit (1 mark)