![[ICO]](/icons/blank.gif) | Name | Last modified | Size | Description |
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![[PARENTDIR]](/icons/back.gif) | Parent Directory | | - | |
![[ ]](/icons/layout.gif) | lec14.pdf | 2017-06-14 08:32 | 128K | 14 - Programmable Logic Applications and Architectures |
![[ ]](/icons/layout.gif) | lec13.pdf | 2017-06-14 08:32 | 45K | 13 - Timing Analysis |
![[ ]](/icons/layout.gif) | lec12.pdf | 2017-06-14 08:32 | 320K | 12 - ELEX 7660 Project FAQ - Part 1 |
![[ ]](/icons/layout.gif) | lec11.pdf | 2017-06-14 08:32 | 46K | 11 - Metastability and Clock Domain Crossing |
![[ ]](/icons/layout.gif) | lec10.pdf | 2017-06-14 08:32 | 61K | 10 - Specifying Timing Constraints |
![[ ]](/icons/layout.gif) | lec9.pdf | 2017-06-14 08:32 | 50K | 9 - State Machine Design |
![[ ]](/icons/layout.gif) | lec8.pdf | 2017-06-14 08:32 | 27K | 8 - Timing Basics |
![[ ]](/icons/layout.gif) | lec7.pdf | 2017-06-14 08:32 | 90K | 7 - Verification |
![[ ]](/icons/layout.gif) | lec6.pdf | 2017-06-14 08:32 | 30K | 6 - Common HDL Constructs (Part 2) |
![[ ]](/icons/layout.gif) | lec5.pdf | 2017-06-14 08:32 | 28K | 5 - Common HDL Constructs |
![[ ]](/icons/layout.gif) | lec4.pdf | 2017-06-14 08:32 | 65K | 4 - Verilog Statements |
![[ ]](/icons/layout.gif) | lec3.pdf | 2017-06-14 08:32 | 771K | 3 - Verilog Expressions |
![[ ]](/icons/layout.gif) | lec2.pdf | 2017-06-14 08:32 | 117K | 2 - RTL Design |
![[ ]](/icons/layout.gif) | lec1.pdf | 2017-06-14 08:32 | 117K | 1 - Introduction to Digital Design with Verilog HDL |
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