![]() | Name | Last modified | Size | Description |
---|---|---|---|---|
![]() | Parent Directory | - | ||
![]() | lec1.pdf | 2000-09-06 16:59 | 91K | Introduction to Logic Design with VHDL |
![]() | outline.pdf | 2000-09-06 16:59 | 17K | Course Outline |
![]() | lec2.pdf | 2000-09-19 16:24 | 96K | 386SX Processor Bus/Instruction Set |
![]() | lec3.pdf | 2000-10-04 15:27 | 255K | RTL Design with VHDL |
![]() | midterm.pdf | 2000-10-24 14:03 | 19K | Mid-Term Exam |
![]() | midsol.pdf | 2000-10-24 14:09 | 11K | Mid-Term Exam Solutions |
![]() | lec4.pdf | 2000-10-27 12:18 | 65K | Interrupts |
![]() | lec10.pdf | 2000-11-08 05:24 | 23K | |
![]() | lec5.pdf | 2000-11-10 12:28 | 216K | Memory, Timing Analysis |
![]() | asm1.pdf | 2000-11-20 13:29 | 26K | Assembly Language |
![]() | lec6.pdf | 2000-11-29 13:23 | 84K | DMA, Buses |
![]() | exam.pdf | 2000-12-11 19:53 | 133K | Final Exam |