Guy is a Professor in Computer Engineering at the University of British Columbia University of British Columbia where he teaches advanced digital design and computer systems/architecture related courses. His research focuses on improving FPGA devices and CAD tools, in particular making them easier to use and more efficient for computing tasks. His research has shown how to design FPGA interconnect to be more efficient, that CAD tool performance can be enhanced through parallelism, and that overlays are a much easier way to program FPGAs . His latest research is attempting to make machine learning and artificial intelligence applications more efficient on FPGAs through low-precision arithmetic, such as TinBiNN for binary neural networks, and using custom accelerator interfaces.
Prof. Lemieux graduated from University of Toronto where he was part of a team that designed NUMAchine, a cache-coherent multiprocessor built from scratch using MIPS R4400 CPUs, custom PCBs and FPGAs. Throughout his career, he's designed or co-designed various soft processors and accelerators (MIPS and NIOS clones, VIPERS, VEGAS, VENICE, ORCA RISC-V, and Saturn-V) and co-founded VectorBlox Computing which developed the MXP (Matrix Processor), a tensor accelerator. Within RISC-V International, he is an elected member of the Technical Steering Committee and chair of the SoftCPU Special Interest Group . Throughout the COVID-19 pandemic, he worked with a small team from the SIG to develop new technology for managing custom instructions without namespace collisions in the ISA, resulting in Google's CFU-Playground as well as CFU interfaces in Lattice's RISC-V RX IP core and Efinix's Titanium FPGAs. After extending this further to provide virtualization and protection (like virtual memory), it is being offered as a basis specification for the new Composable Extensions (CX) Task Group which he helped launch. He was also a member of the RISC-V Vector and the early Cache Management Operations committees. Finally, he serves as a Voting Member and Editor within the Working Group for IEEE P3109 Standard for Arithmetic Formats for Machine Learning which has been releasing updates through its Interim Report.
FPGAs, short for Field-Programmable Gate Arrays, are are universal logic chips, capable of emulating any other digital chip. Of course, this emulation capability comes with some overhead in the form of cost and performance -- a key goal of Prof. Lemieux's research is to drive down the cost as well as improve the speed and power dissipation of these chips. He has done this through optimization at various levels including the transistor-level design, architecture (internal organization) of the device, and CAD tools that map circuits into the device.
Prof. Lemieux is especially interested in the acceleration of compute-oriented applications using custom hardware. For this purpose, FPGAs have shown much promise, but they also have a reputation for being very difficult to "program", particularly among software-oriented designers, the key users in such applications. To help, he is a strong advocate for the use of overlay architectures, which are digital circuits built on top of FPGAs that make them easier to program. Overlays are like a new type of FPGA, in that they themselves are programmable, but they are more application-specific and have fewer users, making them unlikely to be built as custom chips. Nevertheless, his research has shown that regular C programs can be easily mapped to processor-like overlays and offer levels of performance that competitive with GPUs.
His startup, VectorBlox Computing, was acquired by Microchip in September 2019 and is now called the VectorBlox Accelerator SDK . VectorBlox designed a vector accelerator system known as the VectorBlox MXP (MatriX Processor) that operates directly on 1D, 2D and 3D tensors. MXP provides four key architectural features that provide gains in efficiency: scratchpad, hardware DMA, sub-word SIMD, and custom instructions. Instead of a traditional named vector register, MXP uses an addressable scratchpad. Being addressable, vectors are simply pointers in C; this allows any number of vectors of arbitrary length to be formed without any internal fragmentation, reduces the need for data duplication and data movement, and allows use of a stack-based ABI for nesting accelerated vector functions. Hardware DMA makes efficient use of a wide, dedicated path to external memory for transfering 1D and 2D tensors and operates concurrently with computation. Sub-word SIMD provides increased parallelism for operations on byte and halfword elements. Custom instructions make it easy to attach highly pipelined hardware into a C-programmed environment, where the hardware design effort focuses on data operations not on data storage/staging/movement (which is left within C). Furthermore, the MXP is fully portable, allowing the use of almost any host processor and almost any C compiler without the need for any compiler modifications. VectorBlox measured nearly 10,000 times speedup on an N-body physics problem. With this level of acceleration, compiler autovectorization is almost useless because it demands careful planning of code structure and data layout which are best done manually using compiler intrinsics.
His work on interconnect design for FPGAs resulted
in a book, published in November 2003.
He received a
Best Paper
Award at the
2004 IEEE International Conference on Field-Programmable Technology.
His 2001 paper
Using Sparse Crossbars within LUT Clusters
is included as part of FPGA20, the
Top 25 contributions in the First 20 Years
of the International Symposium on FPGAs
between 1992 and 2011.
His 2017 paper
Real-time Object Detection in Software with Custom Vector Instructions and Algorithm Changes,
was nominated for best paper. The accompanying
face detection demo
clearly demonstrates its overall accuracy and speed. This work shows how
success can be achieved using software-first overlay approach; the entire
application was coded in C++ and used less than 300 lines of custom VHDL, but
it out-performed all prior art including custom-built chips dedicated to that
purpose.
