Manuals >Nonlinear Device Models Volume 1 >Curtice GaAs MESFET Characterization
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Model Parameters

Curtice GaAs MESFET model parameters are summarized in the following table. Table 89 lists the parameters with descriptions and default values. Setup attributes are listed in Table 90.

Table 88 Summary of Curtice GaAs MESFET Model Parameters
Parameter Type
Controlling Model Parameters
Inductance and Resistance
LD, LG, LS, RD, RG, RS
Diode
IS, VBI, N
Threshold
Level 1: VTO
Level 2: A0, A1, A2, A3
Linear and Saturation
Level 1: BETA, LAMBDA, ALPHA
Level 2: BETA, GAMMA
Capacitance and AC
CGDO, CGSO, CDS, RDSO, RIN, A5
optionally: CGD, CGS, TAU

Table 89 Curtice GaAs MESFET Model Parameters 
Name
Description
Default
Inductance and Resistance Parameters
LD
Drain Inductance. Specifies external drain inductance.
0 Henry
LG
Gate Inductance. Specifies external gate inductance.
0 Henry
LS
Source Inductance. Specifies external source inductance.
0 Henry
RD
Drain Resistance. Specifies external drain resistance.
0 Ohm
RG
Gate Resistance. Specifies external gate resistance.
0 Ohm
RS
Source Resistance. Specifies external source resistance.
0 Ohm
Diode Parameters
IS
Diode Reverse Saturation Current.    Models gate-drain and gate-source current.
1 x 10-14 Amp
VBI
Gate Junction Potential.    Models built-in potentials of gate-source and gate-drain regions.
0.8 Volt
N
Diode Emission Coefficient.    Models emission coefficient of an ideal diode. In TECAP and some simulators this parameter is called XN.
1.0
XTI
Diode Saturation Current.    Temperature Coefficient.
3.0
EG
Diode Energy Gap
1.11 EV
DC Parameters: Level 1 (Quadratic)
ALPHA
Coefficient of VDS.    It is the Vds coefficient in the tanh function of the quadratic equation.
2.0 V-1
BETA
Transconductance Parameter.    Defines transconductance in the saturation or linear operating regions. Same as JFET model. In TECAP and some simulators this parameter is called BETA1 for level 1, and BETA2 for level 2.
1 x 10-4 AÞV-2
LAMBDA
Channel Length Modulation Parameter.    Models the finite output conductance of a MESFET in the saturation region.
0V-1
VTO
Threshold Voltage.    Models gate turn-on voltage. Same as JFET model.
0V
DC Parameters: Level 2 (Cubic)
GAMMA
Coefficient of VDS.    It is the Vds coefficient in the tanh function of the cubic equation.
0.5V-1
BETA
Coefficient for pinchoff.    Defines change with respect to VDS In TECAP and some simulators this parameter is called BETA1 for level 1, and BETA2 for level 2.
1 x 10-4 A·V-1
A0
0-Order Coefficient for V1 in IDS cubic equation.
1 x 10-2 Amp
A1
1st-Order Coefficient for V1 in IDS cubic equation.
1 x 10-3 A·V-1
A2
2nd-Order Coefficient for V1 in IDS cubic equation.
-1 x 10-3 A·V-2
A3
3rd-Order Coefficient for V1 in IDS cubic equation.
-1 x 10-4 A·V-3
VDSO
Value of VDS at which A0 through A3 are determined
5.0 Volt
RDSO
Internal Resistance.    Drain to Source AC Leakage Path. In TECAP and some simulators this parameter is called RDS
1 x 1012 Ohm
VDSDC
VDS Bias at which RDSO, CGD and CGS are determined
0V
AC and Other Common Parameters
A5
Proportionality Constant.    Varies TAU as a function of VDS. Use TAU for constant time delay or A5 to vary delay as a function of VDS.
0 S·V-1
TAU
Internal Time Delay.    Constant internal time delay from drain to source.
0 Sec
VBR
Reverse Breakdown Voltage.    From gate to drain.
100V
RIN
Series Resistance.    In series with CGS. Used to model the change in input impedance with frequency.
0 Ohm
Piecewise Linear Current Parameters
R1
Approximate Breakdown Resistance.    R1 is the breakdown resistance from drain to gate.
0 Ohm
R2
Resistance Relating Breakdown Voltage.    R2 is the resistance relating breakdown voltage to channel current.
0 Ohm
RF
Effective Value.    RF if the effective value of forward-bias resistance gate to source.
0 Ohm
Constant Capacitance Parameters
CGD
Gate to Drain Capacitance
0 Farad
CGS
Gate to Source Capacitance
0 Farad
CDS
Drain to Source Capacitance
0 Farad
FC
Coefficient for forward-bias depletion capacitance
0.5
Non-Linear Capacitance Parameters
CGDO
Zero bias Junction Capacitance.    Non-linear Gate to Drain Capacitance at zero DC bias.
0 Farad
CGSO
Zero bias Junction Capacitance.    Non-linear Gate to Source Capacitance at zero DC bias.
0 Farad

Table 90 Setup Attributes for the Curtice GaAs Model 
DUT/
Setup

Inputs
Outputs
Transform
Function
Extractions
ac/
s_at_f

vg, vd, vs, freq
s
extract_L_and_R
GAASAC_l_and_r
LD, LG, LS, RD, RG, RS
dc/
igvg_0v[sd]

vg, v[sd]
ig
extract
GAASDC_lev1
VBI, IS, N
optim1
Optimize
VBI, IS, N
dc/
idvg_hi_vd

vg, vd, vs
id, ig
extract


GAASDC_cur1
Level 1: VTO
Level 2: A0, A1, A2, A3
optim
Optimize
Level 1: VTO
Level 2: A0, A1, A2, A3
dc
vd, vg, vs
id, ig
extract
GAASDC_cur2
Level 1: BETA, ALPHA, LAMBDA
Level 2: BETA, GAMMA
optim
Optimize
Level 1: BETA, ALPHA, LAMBDA
Level 2: BETA, GAMMA
ac
vg, vd, vs, freq
s
extract_CV
GAASC_cur
CGDO, CGSO, CDS, RDSO, RIN, A5
optionally: CGS, CGD,TAU


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