Capacitance Model

Please use the model bsim3_tutor_cv.mdl provided with the BSIM3v3 Modeling Package to visualize the capacitance model parameters. Load the file into IC-CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor.

The capacitance in a MOS transistor can be divided into three different parts:

These different parts of the capacitance of a MOS transistors are shown in the following figure. The following three sections explain each type of capacitance and its implementation in the BSIM3v3 model.

Figure 102 Different Parts of the Capacitance of a MOS Transistor

Junction Capacitance

The source/drain-bulk junction capacitance can be divided into three components as shown in the following figure. The calculation is shown for the drain-bulk junction capacitance. The source-bulk capacitance is calculated in the same way with the same model parameters.

The overall junction capacitance C_jdb is given by:

(93)

where:

C_AREA is the bottom area capacitance

C_SW is the sidewall or peripheral capacitance along the three sides of the junction's field oxide

C_SWG is the sidewall or peripheral capacitance along the gate oxide side of the junction

Figure 103 Dimensions of Drain/Source Region and Different Capacitance Parts

Bottom area capacitance C_AREA

(94) C_AREA = AD*C_jbd

where:

AD area of bottom side of pn junction, given as SPICE model parameter

C_jbd capacitance per unit area of the drain-bulk junction

C_jbd is calculated according to the following equation and is shown in the following figure.

For V_bs < 0:

(95)

For V_bs 0:

Figure 104 Bottom Area Capacitance C_jbd as a Function of V_g

Peripheral sidewall capacitance C_SW along the field oxide

(96) C_SW = (PD - W_eff)C_jbdsw

where:

PD	total perimeter of pn junction, given as SPICE model parameter
Weff	effective gate width of transistor, calculated in SPICE
Cjbdsw	capacitance per unit length

C_jbdsw is calculated according to the following equation and is shown in the following figure:

For V_bs < 0:

(97)

For V_bs 0:

Figure 105 Sidewall Capacitance C_jbdsw as a Function of V_g

Peripheral sidewall capacitance C_SWG along the gate oxide

(98) C_SWG = W_effC_jbdswg

where:

Weff	effective gate width of transistor, calculated in SPICE
Cjbdswg	capacitance per unit length

C_jbdswg is calculated according to the following equation and is shown in the following figure.

For V_bs < 0:

(99)

For V_bs 0:

Figure 106 Sidewall Capacitance C_jbdswg Along the Gate Oxide as a Function of V_g

Extrinsic Capacitance

As mentioned in the introduction to this chapter, the extrinsic capacitance of a MOS transistor consists of the following three components:

The contribution of these different components to the overall extrinsic capacitance is demonstrated in the following figure and Figure 108.

Figure 107 Different Components of the Extrinsic Capacitance

Figure 108 Overlap Capacitance Between Gate and Drain/Source/Bulk

a) Fringing Capacitance

The fringing capacitance of a MOS transistor consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. In the present release of the BSIM3v3 model, only the bias independent outer fringing capacitance is implemented. Experimentally, it is virtually impossible to separate this capacitance with the overlap capacitance. Nonetheless if the model parameter CF is not given, the outer fringing capacitance can be calculated with the following equation:

(100)

b) Overlap Capacitance

In BSIM3v3 an accurate model for the overlap capacitance is implemented. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure, the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, this region can be modeled with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of overlap capacitance. This LDD region can be in accumulation or depletion.

In BSIM3v3, a single equation is implemented for both regions by using such smoothing parameters as Vgs_overlap and Vgd_overlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgs_overlap = Csg_overlap and Cgd_overlap = Cdg_overlap.

The model equations for the overlap capacitance are shown for the drain overlap capacitance and are identical for the source overlap capacitance:

Overlap charge per gate width:

(101)

where:

with the smoothing parameter:

(102)

for the measurement and simulation conditions given in Figure 107, this results in the overlap capacitance:

(103)

The model parameter CGDO in Equation 101 can be calculated by the following equation:

(104)

where DLC represents the channel length reduction in the BSIM3v3 capacitance model. Please see the next section for more details about DLC:

Intrinsic Capacitance

a) Geometry for Capacitance Model

The BSIM3v3 model uses different expressions for the effective channel length L_eff and the effective channel width W_eff for the I-V and the C-V parts of the model.

The geometry dependence for the intrinsic capacitance part is given as the following:

(105)

(106)

L_active and W_active are the effective length and width of the intrinsic device for capacitance calculations. The parameter ΔL is equal to the source/drain to gate overlap length plus the difference between drawn and actual poly gate length due to processing (gate printing, etching, and oxidation) on one side. The L_active parameter extracted from the capacitance method is a close representation of the metallurgical junction length (physical length).

(107)

(108)

Figure 109 Dimensions of a MOSFET

While the authors of the BSIM3v3 model suggest to use a parameter LINT for the I-V model, which is different from DLC, other literature sources [3] propose that LINT should have the same value as DLC. This approach is also implemented in the BSIM3v3 Modeling Package to ensure that the extracted values of the channel length reduction are very close to the real device physics. Therefore, the channel length reduction LINT for the I-V model will be set to DLC from the C-V model extracted from capacitance measurements.

b) Intrinsic Capacitance Model

The intrinsic capacitance model that is implemented in the BSIM3 model is based on the principle of conservation of charge. There are a few major considerations in modeling the intrinsic capacitance of a deep submicron MOS transistor:

Therefore, this section presents no details about the intrinsic charge formulations. Please refer to the BSIM3v3 manual [1] for more information. Only the basic principles are described here.

To ensure charge conservation, terminal charges instead of the terminal voltages are used as state variables. The terminal charges Q_g, Q_b, Q_s, and Q_d are the charges associated with the gate, bulk, source, and drain. The gate charge is comprised of mirror charges from 3 components:

The accumulation charge and the substrate charge are associated with the substrate node while the channel charge comes from the source and drain nodes:

(109)

The inversion charges are supplied from the source and drain electrodes. The ratio of Q_d and Q_s is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (given by the model parameter XPART = 0, 0.5, and 1) which are the ratios of Q_d to Q_s in the saturation region.

From these four terminal charges, 9 transcapacitances C_{(terminal,voltage)} are calculated inside the BSIM3 model as partial derivatives with respect to the voltages V_gb, V_db, and V_sb. The abbreviation can be interpreted as:

C_ggb ..... partial derivative of Q_g with respect to V_gb

Partial derivatives of Q_g:

(110)

Partial derivatives of Q_d:

(111)

Partial derivatives of Q_b:

(112)

The 9 transcapacitances previously introduced are shown in the following three plots for a simulation setup as shown in the following figure:

Figure 110 Simulation and Measurement Setup for Overlap Capacitances

Figure 111 Terminal charges Q_g, Q_b and Q_d

Figure 112 Partial derivatives of Q_g, Q_b and Q_d with respect to V_db, V_gb and V_sb

The Overall Capacitance in BSIM3

In previous sections, the three components of the BSIM3 capacitance model were introduced. Now when an AC simulation is performed the capacitance, which can be measured at the terminals, is composed of different parts of junction capacitances, extrinsic capacitances, and intrinsic capacitances.

The following figure shows, as an example, the capacitance components for the overlap capacitance between gate and bulk/source/drain as simulated according to the following circuit description:

Figure 113 Different Parts of Overlap Capacitance C_Gate_SDB

The overlap capacitance C_Gate_SDB consists of:

(113)

where:

Cggb	intrinsic capacitance
Cgd,overlap	overlap capacitance between gate and drain
Cgs,overlap	overlap capacitance between gate and source
Cgb,overlap	overlap capacitance between gate and bulk

Other capacitances can be calculated in the same way. Please refer to the BSIM3 manual for more details.