Test Structures for Deep Submicron CMOS Processes

Manuals >Nonlinear Device Models Volume 1 >BSIM4 Characterization Print version of this Book (PDF file)

Test Structures for Deep Submicron CMOS Processes A very important prerequisite for a proper model parameter extraction is the selection of appropriate test structures. Chapter 5, "BSIM3v3 Characterization" contains detailed descriptions of appropriate test structures for deep submicron MOS transistors. See Table 66 for an example. A detailed description of ideal test structures is located in the JESSI AC-41 reports [2].