Eddie Hung

Adjunct Professor within the System-on-Chip research group,
in the Electrical and Computer Engineering Department
at The University of British Columbia

Contact address: <username>@ece.ubc.ca, where my username is eddieh

You can find out what I'm working on at http://github.com/eddiehung and http://eddiehung.github.io,
from where you can also find the latest version of VTR-to-Bitstream.

My PhD thesis was titled: Harnessing FPGA technology for rapid circuit debug.

• Our tool for using a Virtual Overlay Network for FPGA Trace Buffers, Quick-Trace, available here.
  
• Our VTR-to-Bitstream patch v1.1 for VTR v1.0 is available here.
  
• Our incremental signal tracing tool, Inc-Trace, is available for download here.
• Our speculative debug insertion tool, In-Spec, is available for download here.
• Our delay model from "A Detailed Delay Path Model for FPGAs" is available for download here.

Unofficial Doxygen-generated documentation of:

• VPR 6.0 -- [Part of The Verilog-to-Routing (VTR) Project http://code.google.com/p/vtr-verilog-to-routing/]
• VPR 5.0 -- [http://www.eecg.utoronto.ca/vpr/]
• ABC -- [http://www.eecs.berkeley.edu/~alanmi/abc/]
• VIS/GLU -- [http://vlsi.colorado.edu/~vis/]
• ODIN-II -- [http://code.google.com/p/odin-ii]

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