Previously, I was a PhD student supervised by Professor Steve Wilton,
and also a post-doc within this department and at Imperial College London.
Contact address: <username>@ece.ubc.ca, where my username is eddieh
You can find out what I'm working on at http://github.com/eddiehung and http://eddiehung.github.io,
from where you can also find the latest version of VTR-to-Bitstream.
My PhD thesis was titled: Harnessing FPGA technology for rapid circuit debug.
- Our tool for using a Virtual Overlay Network for FPGA Trace Buffers, Quick-Trace, available here.
- Our VTR-to-Bitstream patch v1.1 for VTR v1.0 is available here.
- Our incremental signal tracing tool, Inc-Trace, is available for download here.
- Our speculative debug insertion tool, In-Spec, is available for download here.
- Our delay model from "A Detailed Delay Path Model for FPGAs" is available for download here.
Unofficial Doxygen-generated documentation of: