In-Spec :: Speculative Debug Insertion Tool for FPGAs
Published at FPL 2011, PDF.
In-Spec is a one-click speculative debug insertion tool that will
automatically instrument your Altera Quartus II project using SignalTap II.
Requirements: Altera Quartus II, SignalTap II, Python with the networkx package.
- Unzip the downloaded file into the directory containing your Quartus II
- Open up 'Makefile' and modify the variables as appropriate
- Type 'make' and go for a cup of tea! When it's done, your speculatively
instrumented should be in the 'debug' sub-directory
- Your project must contain an SDC constraints file with a create_clock
constraint for the main clock, otherwise Fmax will not be calculated
for the instrumented design
- In-Spec has only been tested with Quartus v11.0 targeting Stratix III
We would like to keep track of how many research groups are using this tool,
so we would really appreciate it if you could fill out the following information: