Quick-Trace :: A Virtual Overlay Network for FPGA Trace Buffers

Eddie Hung, Steven J. E. Wilton

Published at FPGA 2013, PDF.
Extended for TODAES, PDF (pre-print).

Quick-Trace implements the incremental signal-tracing techniques presented in
our FPGA'13 paper on the VPR6 CAD tool, part of the Verilog-To-Routing academic toolflow.
This was subsequently extended for the TODAES journal, where the key improvement
have been to extend the overlay network concept to triggering.

Quick-Trace v2.0 is supplied as a patch for VTR version 1.0:

The overlay network can be enabled using VTR's own ./run_vtr_flow.pl script,
which has been augmented with three new stages:

• "overlay" -- installs the overlay network which connects as many combinational or
  sequential signals to the free memory blocks of the circuit
• "match" -- which matches a set of randomly-selected trigger/trace signals to this network
  In particular, this calls our "mwbm" tool (C++) supplied to find a maximum-weighted bipartite match for the overlay network.
• "collapse" -- which takes the matchings from the previous stage, and collapses the
  overlay network into valid VPR routing (just as if you did incremental-tracing)

Dependencies:

• LEMON Graph library which provides the maximum weighted bipartite matching functions used in the "match" stage.

Changelog:

• v2.0 -- Jan 2014: Initial release
• v1.0 -- Feb 2013: Internal release

We would like to keep track of how many research groups are using this tool, so we would really appreciate it if you could fill out the following information: