A Detailed Delay Path Model for FPGAs

Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip H. W. Leong

Published at FPT 2009, PDF

Our delay model is provided in the form of an easy-to-use Excel spreadsheet.

Key Features:

• A complete delay model, combining our transistor-level model
  with the wirelength model from [Smith et al.] and the circuit depth
  model from [Das et al.]
• Extensible, allowing user-defined circuits and process technologies
  to be added easily
• Parameter sweep capability, allowing a user to sweep any two
  FPGA parameters across any values, over the MCNC20 (or any other)
  set of circuits

We would like to keep track of how many research groups are using this model,
so we would really appreciate it if you could fill out the following information: