Inc-Trace :: Incremental Signal-Tracing for FPGA Debug

Eddie Hung, Steven J. E. Wilton

Published at FPL 2012, PDF.
Extended for TVLSI, PDF.

Inc-Trace implements the incremental signal-tracing techniques presented in
our FPL'12 paper on the VPR6 CAD tool, part of the Verilog-To-Routing academic toolflow.
This was subsequently extended for the TVLSI journal, where the key improvement
have been a timing-driven directed search strategy (100X faster than the original
breadth-first approach).

Inc-Trace v2.0 is supplied as a patch for VTR version 1.0:

Unpack VTR (into the vtr_release/ directory), copy the patch file inside, and then apply the patch by typing:

Incremental-tracing can be enabled using VTR's own ./ script,
which has been augmented with a new "trace" stage, as well as other nice things.
This new stage reads the packed-place-routed circuit, and incrementally traces a randomly-selected
fraction of all signals to connect to the leftover memory capacity.

N.B.: By default, this script applies "--allow_unrelated_clustering off" to VPR. To reproduce results from our TVLSI paper, add the "-vpr_unrelated_clustering on" switch to the script above.

The extra incremental-tracing options now supported in VPR6 are:


We would like to keep track of how many research groups are using this tool, so we would really appreciate it if you could fill out the following information: