VTR-to-Bitstream

Eddie Hung, Fatemeh Eslamy, Steven J. E. Wilton

Published at FCCM 2013, PDF.

VTR-to-Bitstream is supplied as a patch for VTR version 1.0:

Unpack VTR (into the vtr_release/ directory), copy the patch file inside, and then apply the patch by typing: Currently, this release supports only the xc6vlx240tff1156-1ffg1156 Virtex-6 device found on the popular ML605 evaluation kit.
Other devices may be supported in the future, but if you're an eager one, then I'd be happy to assist you in doing so.

Dependencies:

Xilinx ISE supporting the ML605 device (full license; WebPack won't cut it, I'm afraid)
Java
RapidSmith (to be unpacked into the vtr_release/ directory)

To run the entire flow from Verilog to Bitstream, use VTR's own ./run_vtr_flow.pl script,
which has been augmented with a new "bitstream" stage, as well as other nice things.
This new stage performs VTR->XDL translation, using a Java application (rather poorly written, sorry,
I'm not much of Java person) and RapidSmith, and then runs the vendor tools.

The secret sauce of this project is mainly in two files:

bitstream/xc6vlx240ttf1156.java
Java application which reads in the .blif (LUT masks, RAM/DSP instantiations), .net (packed netlist)
and .place (placement locations) output files from VTR and transforms them into an exact
Xilinx XDL netlist (utilizing RapidSmith API).
vtr_flow/arch/xilinx/xc6vlx240tff1156.xml
VPR6.0 architecture file that describes the Virtex-6 CLB, the precise location of all I/O, RAM
and DSP columns, as well as empty regions in the fabric.

Changelog:

v1.1 -- October 2013: Minor release;
- Add example benchmark 'counter.v' (simple fast/slow up/down 8 bit counter)
  To build the counter.v design, enter vtr_flow/scripts and enter:
  
  ./run_vtr_flow.pl ../benchmarks/verilog/counter.v ../arch/xilinx/xc6vlx240tff1156.xml -vpr_fix_pins ../arch/xilinx/ml605.ioplace
- Add support for translating UCF pin constraints to VPR constraints
  Example usage:
  
  ./ucf2ioplace.py ML605.ucf ../arch/xilinx/xc6vlx240tff1156.ioplace > ../arch/xilinx/ml605.ioplace
  (ML605.ucf available from Xilinx here)
- Add support for RAMB18 36x512 mode
v1.0 -- April 2013: Initial release

We would like to keep track of how many research groups are using this tool, so we would really appreciate it if you could fill out the following information:

Unfortunately, there is a bug in ODIN-II regarding inferred multipliers which causes VTR to fail on this architecture for benchmarks diffeq{1,2}.v (and maybe others). You can follow the bug report here.

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