Circuit Description Syntax

This section describes basic syntax rules for creating a circuit description.

SPICE Simulators

Start an input line with * to denote a comment in the circuit model description or in the input file of the simulation debugger. Although some simulators accept # and * , IC-CAP accepts * only. (# is recognized as a preprocessor directive when the simulator input deck is built. Adding a comment using # causes a simulation generated from a DUT or Setup to fail.)

The following table lists the SPICE element component specifications. For information on available options and their syntax, refer to the SPICE Reference manual.

Table 65 lists the semiconductor device specifications. For information on available options and their syntax, refer to the SPICE Reference manual.

Table 64 SPICE Element Component Specifications 

Component	General Form	Example
Resistor	RXXXXXXX N1 N2 VALUE <TC=TC1<TC2>>	R1 1 2 1000 TC=0.001,0.015
Capacitor	CXXXXXXX N+ N- VALUE <IC=INCOND>	COSC 15 2 10U IC=3
Inductor	LXXXXXXX N+ N- VALUE <IC=INCOND>	LSHUNT 3 29 10U IC=15.7m
Mutual Inductor	KXXXXXXX LYYYYYYY LZZZZZZZ VALUE	K43 LAA LBB 0.999
Transmission Line	TXXXXXXX N1 N2 N3 N4 Z0=VALUE <TD=VALUE>+ <F=FREQ <NL=NRMLEN>> <IC=V1,I1,V2,I2>	T1 1 0 2 0 Z0=50 TD=10NS
Linear Voltage- Controlled Current Source	GXXXXXXX N+ N- NC+ NC- VALUE	G1 2 0 5 0 0.1M
Linear Voltage- Controlled Voltage Source	EXXXXXXX N+ N- NC+ NC- VALUE	E1 2 3 14 1 2.0
Linear Current- Controlled Current Source	FXXXXXXX N+ N- VNAM VALUE	F1 13 5 VSENS 5
Linear Current- Controlled Voltage Source	HXXXXXXX N+ N- VNAM VALUE	HX 5 17 VZ 0.5K
Independent Voltage Source	VXXXXXXX N+ N- <<DC> DC/TRAN VALUE> + <AC <ACMAG <ACPHASE>>>	VIN 12 0 DC 6
Independent Current Source	IXXXXXXX N+ N- <<DC> DC/TRAN VALUE> + <AC <ACMAG <ACPHASE>>> + SFFM(0 1 10K 5 1K)	ISRC 23 21 AC 0.333 45.0

Table 65 SPICE Semiconductor Component Specifications 

Component	General Form	Example
Junction Diode	DXXXXXXX N1 N2 MNAME + <AREA><OFF><IC=VD>	DCLAMP 3 7 DMOD 3.0 IC=0.2
BJT	QXXXXXXX NC NB NE <NS> MNAME + <AREA> <OFF> <IC=VBE,VCE>	Q2A 11 26 4 20 MOD1
JFET	JXXXXXXX ND NG NS MNAME + <AREA> <OFF> <IC=VDS,VGS>	J1 7 2 3 JM1 OFF
MOSFET	MXXXXXXX ND NG NS NB MNAME + <L=VAL><W=VAL><AD=VAL><AS=VAL> +<PD=VAL><PS=VAL><NRD=VAL><NRS=VAL> + <OFF> <IC=VDS,VGS,VBS	M1 2 9 3 0 MOD1 L=10U W=5U

HSPICE Simulator

Basic HSPICE syntax rules are the same as SPICE-type simulators. Refer to the HSPICE User's Manual for complete syntax and rules.

ELDO Simulator

Basic ELDO syntax rules are the same as SPICE-type simulators. In addition to the SPICE-type syntax, FAS user-defined models can be defined and instantiated in the IC-CAP Circuit Editor. An FAS model is defined as:

 amodel name(pin1,pin2..)
.
<model body> 
. 
endmodel

(smodel and fmodel are also accepted).

The above model is instantiated in a circuit as:

 yxx name [pin:] 1 2 ... [param: par1 = var1 ...] [model: ...]

In addition, the parser accepts the following ELDO constructs:

 .ADDLIB number pathname
#com . . #endcom

FIDEL models (oxx p1:typ p2:typ ... mod=modelname) and transfer functions (FNS, FNZ) are not currently supported by the IC-CAP parser. However, the #echo keyword can be used to insert these statements into a circuit in the IC-CAP Circuit Editor.

The #echo keyword is available in the IC-CAP Circuit Editor for all supported simulators. #echo can be used to pass a deck card or command directly through to the simulator without any parsing by IC-CAP. For example, the line

 #echo <something that the IC-CAP parser doesn't understand>

is sent to the simulator as

 <something that the IC-CAP parser doesn't understand>

The following analog model instantiation syntax is supported for HDL-A:

HDL-A user-defined models with the following syntax can also be instantiated in the IC-CAP Circuit Editor.

 yxx name(xx) [pin:] 1 2 ... [param: par1 = var1 ...]

and

 yxx name(xx) [pin:] 1 2 ... [generic: par1 = var1 ...]