MOSFET Model Parameters
The following table lists parameters for the three model levels according to DC and cv extraction in IC-CAP. (Some of these parameters are redundant and therefore only a subset of them is extracted in IC-CAP.) Table 76 describes model parameters by related categories and provide default values. The parameter values are displayed in the Circuit folder. Table 77 lists setup attributes.
Table 75 Summary of UCB MOSFET Controlling Model Parameters
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Classical
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VTO, GAMMA, PHI KP IS, JS, TOX
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NSUB, UO, UCRIT, UEXP, UTRA, NFS, NSS, TPG
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NSUB, UO, THETA, NFS, NSS, TPG
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Short-channel
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LD, XJ
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LD, XJ
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Narrow-width
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DELTA, WD†††
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Saturation
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LAMBDA
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NEFF, VMAX
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ETA, KAPPA
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External resistance
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NRD††, NRS†† RD, RS
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Junction capacitance
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AD††, AS††, CBD, CBS CJ, FC, MJ, PB
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Sidewall capacitance
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PD††, PS††, CSJW, MJSW
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Overlap capacitance
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CGBO, CGDO, CGSO
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General
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LEVEL, L††, W††
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IC-CAP Temperature Specification
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TNOM (system variable)
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Notes:
† LEVEL 2 and LEVEL 3 also include LEVEL 1 parameters.
†† Indicates device parameters (model and device parameters are listed together).
††† WD does not exist in the SPICE UCB version; it has been added to some SPICE versions and is included in IC-CAP. If WD is not in your simulator, ignore the result (set to zero), or subtract 2·WD from the channel width. In the MOS model files provided with IC-CAP, the width specification W in each of the DUTs has been modified to subtract the value of 2·WD from the drawn width. WD is specified in Model Variables.
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Table 76 UCB MOSFET Parameters
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Capacitance
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CGBO
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Gate to Bulk Overlap Capacitance. Capacitance due to design rules that require the gate be extended beyond the channel by some amount. Not voltage dependent. Total Cgb capacitance equals Cgbo times channel length.
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0 F/m
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CGDO
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Gate to Drain Overlap Capacitance. Capacitance due to the lateral diffusion of the drain in an Si gate MOSFET. Not voltage dependent. Total Gcd capacitance equals Cgdo times the channel width.
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0 F/m
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CGSO
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Gate to Source Overlap Capacitance. Capacitance due to the lateral diffusion of the source in an Si gate MOSFET. Not voltage dependent because it is not a junction capacitance. Total Cgs capacitance equals Cgso times channel width.
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0 F/m
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CJSW
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Zero Bias Junction Sidewall Capacitance. Models the nonlinear junction capacitance between the drain and the source junction sidewall. (Pd + Ps) * CJSW = total junction sidewall capacitance.
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0 F/m
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MJSW
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Grading Coefficient of Junction Sidewall. Models the grading coefficient for the junction sidewall capacitance.
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0.33
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PB
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Bulk Junction Potential. Models the built-in potential of the bulk-drain or bulk-source junctions. The default is usually adequate.
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0.8 volt
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FC
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Forward Bias Non-Ideal Junction Capacitance Coefficient. Models the point (FC * PB) at which junction capacitance makes the transition between forward and reverse bias.
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0.5
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Electrical Process
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IS
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Substrate Junction Saturation Current. Helps model current flow through the bulk-source or bulk-drain junction.
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1×10-16 Amp
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JS
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Substrate Junction Saturation Current/m2. Js equals Is divided by the junction area. For example, Isd=Js*Ad where Ad is the drain area.
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1×10-4 A/m2
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RD
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Drain Ohmic Resistance. This parameter is geometry independent in SPICE and IC-CAP. In fact, it is inversely proportional to channel width.
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0 Ohm
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UCRIT
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Critical Field for Mobility Degradation. Used in level=2 model only.
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1000 V · cm-1
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UEXP
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Critical Field Exponent. Used in level=2 model only.
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0
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UO
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Surface Mobility at Low Gate Levels. Specifies mobility in level=2 and level=3 models. In the level=2 model, if Kp is UTRA
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600 cm2/(V · S)
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UTRA
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Transverse Field Coefficient. Used in level=2 model only. Set UTRA to 0 to obtain same result as SPICE.
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0
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VMAX
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Maximum Drift Velocity of Carriers. Determines whether Vdsat is a function of scattering velocity limited carriers or a function of drain depletion region pinch-off.VMAX is valid only for level=2 and level=3 models. If VMAX is specified, the scattering velocity limited carrier model is used to determine Vdsat.
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0 m · s-1
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NEFF
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Total Channel Charge. A multiplicative factor of NSUB, NEFF determines saturated output conductance. Used only in the level=2 model, and only when Vmax is specified.
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1.0
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Physical Process
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LD
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Lateral Diffusion Coefficient. Used to determine the effective channel length.
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0 Meter
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TOX
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Oxide Thickness. Used when calculating conduction factor, backgate bias effects, and gate-channel capacitances.
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100×10-9 Meter
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TPG
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Type of Gate. Indicates whether gate is of metal or poly-silicon material (0=aluminum; 1=opposite substrate; -1=same as substrate). Used in calculating threshold voltage when Vto is not specified.
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1
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WD
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Channel Width Reduction. Used to determine the effective channel width This parameter is assumed to be 0 in SPICE.
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0 Meter
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XJ
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Metallurgical Junction Depth. Defines the distance into the diffused region around the drain or source at which the dopant concentration becomes negligible. Used to model some short channel effects.
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0 Meter
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Threshold Related
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NFS
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Effective Fast Surface State Density. Used to determine subthreshold current flow. Not valid for extracting simple linear region classical parameters.
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0 cm-2
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NSS
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Effective Surface Charge Density. Used to calculate threshold voltage when Vto is not specified.
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0 cm-2
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NSUB
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Substrate Doping Concentration. Used in most calculations for electrical parameters. It is more accurate to specify Vto rather than deriving it from NSUB. However, NSUB should be specified when modeling the back gate bias dependency of Vto.
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1 × 1015 cm-3
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DELTA
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Width Effect on Threshold Voltage. Used in LEVEL=2 and LEVEL=3 models to shift threshold voltage for different channel widths.
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0
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ETA
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Static Feedback. Used in LEVEL=3 model to decrease threshold for higher drain voltage.
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0
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GAMMA
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Bulk Threshold. The proportionality factor that defines the threshold voltage to backgate bias relationship. Used in the derivation of Vto, Ids, and Vdsat. If not specified in LEVEL=2 and LEVEL=3 models, it is computed from NSUB.
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0 V1/2
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VTO
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Extrapolated Zero Bias. Threshold Voltage Models the onset of strong inversion in the LEVEL=1 model. Marks the point at which the device starts conducting if weak inversion current is ignored.
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0 Volt
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Electrical
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KAPPA
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Saturation Field Factor. Used in the level=3 model to control saturation output conductance.
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0.2
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KP
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Intrinsic Transconductance. If not specified for the level=2 model, KP is computed from Kp=u0*Cox. In some of the literature, KP may be shown as k'. The default for the LEVEL=1 model is 2x10e-5.
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0 A/V2
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LAMBDA
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Channel Length Modulation Models. The finite output conductance of a MOSFET in saturation. It is equivalent to the inverse of Early Voltage in a bipolar transistor. Specifying this parameter ensures that a MOSFET will have a finite output conductance when saturated. In the level=1 model, if lambda is not specified a zero output conductance is assumed. In the level=2 model, if lambda is not specified, it will be computed.
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0 V-1
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PHI
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Surface Potential Models. The surface potential at strong inversion.If not specified in level=2 and level=3 models, it is computed as PHI=2kT/q *ln(Nsub/ni). PHI also may be shown as 2*PHIb.
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0 Volt
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THETA
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Mobility Reduction. Used in level=3 to model the degradation of mobility due to the normal field.
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0 V-1
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Device Geometry
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L
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Drawn or Mask Channel Length. Physical length of the channel.
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1×10-4 Meter
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W
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Drawn or Mask Channel Width. Physical width of channel.
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1×10-4 Meter
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AD
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Area of Drain Area of drain diffusion. Used in computing Is (from Js), and drain and source capacitance from Cbd=CjAd.
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0 m2
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AS
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Area of Source diffusion. Can be used as described for AD.
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0 m2
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NRD
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Equivalent Squares in Drain Diffusion. Number of equivalent squares in the drain diffusion. Multiplied by Rsh to obtain parasitic drain resistance (Rd).
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1.0
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NRS
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Equivalent Squares in Source Diffusion. Number of equivalent squares in the source diffusion. Multiplied by Rsh to obtain parasitic source resistance (Rs).
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1.0
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PD
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Drain Junction Perimeter. Used with CJSW and MJSW to model the junction sidewall capacitance of the drain.
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0 Meter
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PS
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Source Junction Perimeter. Used with CJSW and MJSW to model the junction sidewall capacitance of the source.
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0 Meter
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General
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LEVEL
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Extraction Level. Specifies one of four extraction levels.
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1
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Table 77 MOSFET Setup Attributes
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LEVEL 2 Model
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large/
idvg
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vg, vb, vd, vs
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id
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extract
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MOSDC_lev2_lin_large
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NSUB, UO, UEXP, VTO
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optimize
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NSUB, UO, UEXP, VTO
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narrow/
idvg
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//
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//
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extract
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MOSDC_lev2_lin_narrow
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DELTA, WD
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optimize
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DELTA, WD
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short/
idvg
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//
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//
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extract
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MOSDC_lev2_lin_short
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LD, XJ
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optimize
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LD, RD, RS, XJ
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short/
idvd
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vd, vg, vb, vs
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id
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extract
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MOSDC_lev2_sat_short
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NEFF, VMAX
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optimize
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NEFF, VMAX
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cbd1/
cjdarea
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vb, vd
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cbd
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set_CJ extract
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Program
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initial zero bias CJ
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Optimize
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CJ, MJ, PB
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cbd2/
cjdp3erimeter
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vb, vd
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cbd
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extract
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MOSCV_total_cap
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CJ, MJ, CJSW, MJSW, PB
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LEVEL 3 Model
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large/
idvg
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vg, vb, vd, vs
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id
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extract
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MOSDC_lev3_lin_large
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NSUB, UO, THETA, VTO
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optimize
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NSUB, UO, THETA, VTO
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narrow/
idvg
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//
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//
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extract
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MOSDC_lev3_lin_narrow
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DELTA, WD
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optimize
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DELTA, WD
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short/
idvg
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//
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//
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extract
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MOSDC_lev3_lin_short
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LD, RD, RS, XJ
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optimize
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LD, RD, RS, XJ
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short/
idvd
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vd, vg, vb, vs
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id
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extract
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MOSDC_lev3_sat_short
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ETA, KAPPA
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optimize
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ETA, KAPPA
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cbd1/
cjdarea
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vb, vd
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cbd
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set_CJ
extract
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Program
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initial zero bias CJ
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Optimize
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CJ, MJ, PB
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cbd2/
cjdperimeter
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vb, vd
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cbd
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extract
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MOSCV_total_cap
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CJ, MJ, CJSW, MJSW, PB
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