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RF Circuit used for HiSIM2
The following listing represents a scalable HiSIM2 NMOS-transistor used for RF extraction, complete with extensions to account for parasitic capacitances arising from metal crossovers and inductors to account for device size.
------------------------------------------------------------ ; Scalable subcircuit model for hsim2.4.0 RF n-type devices ; Simulator: Agilent Advanced Design System ; Model: hsim2 Modeling Package ; Date: 11.04.2008 ; Origin: ; ICCAP_ROOT/..../hsim2/circuits/hpeesofsim/cir/rf_nmos_scale.cir ; ------------------------------------------------------------ ; ; --- Information for model implementation --------------- ; In ADS, call the sub circuit model as follows with the ; actual values of L, W, etc. ; hsim2_RF_Extract:x_rf_transistor n1 n2 n3 n4 ; tmp_l=0.25u tmp_w=80u .... ; ; Please note: The parameters tmp_w, tmp_ad, tmp_as, tmp_pd, ; tmp_ps, tmp_nrs, tmp_nrd always define the TOTAL width ; (drain area, ..., number of drain squares) of the multi ; finger device. ; The width (drain area, ..) of a single finger of the ; multifinger MOSFET will internally be calculated by ; Width=tmp_w/tmp_nf. This hsim2 RF model finally uses the ; multiplier "_M" to account for "_M=tmp_nf" number of gate ; fingers (see the call of the MOSFET below). ; define hsim2_RF_Extract (i1 i2 i3 i4) ; ;--- parameters for sub-circuit ---------------------------- parameters tmp_l=1u tmp_w=10e-6 tmp_nf=1 tmp_ad=10e-12 tmp_as=10e-12 tmp_pd=22e-6 tmp_ps=22e-6 tmp_nrd=0 tmp_nrs=0 ngcon=1 ; ;--- hsim2 model card -------------------------------------- ; Parameters for the MOS device
;--- Additional model parameters necessary for scalability-- ; - scalable external capacitors taking into account cross ; coupling between metal lines and inductors to account for ; delay effects due to the size of the devices ; - scalable channel length reduction in multi finger devices ; - a scalable substrate network and scalable Delta L reduction CGDEXT0=1e-9 ;external capacitance gate-drain per gate width and gate finger [F/m] CGSEXT0=1e-9 ;external capacitance gate-source per gate width and gate finger ; [F/m] CDSEXT0=1e-9 ;external capacitance drain-source per gate width and gate finger ; [F/m] RSHG=25 ; gate sheet resistance [Ohm sq] LDRAIN0=1e-6 ; drain inductance per gate width and gate finger [H/m] LGATE0=1e-6 ; gate inductance per gate width and gate finger [H/m] LSOURCE0=1e-6 ; source inductance per gate width and gate finger [H/m] LBULK0=1e-6 ; bulk inductance per gate width and gate finger [H/m] RSHB=25 ; bulk sheet resistance [Ohm sq] DSBC=2e-6 ; distance source implant to bulk contact [m] DDBC=2e-6 ; distance drain implant to bulk contact [m] DGG=2e-6 ; distance gate to gate [m] DL0=0 ; basic channel length reduction correction [m] DL1=0 ; channel length reduction correction 1. and 2. fingers [m] DL2=0 ; channel length reduction correction outer fingers [m] ; ; --- internal temporary variables factor_even_odd = 0.5*(1+(tmp_nf-2*int(0.5*tmp_nf))) tmp_dl1 = (tmp_nf-4.5)/(2*abs(tmp_nf-4.5)) * 8/ tmp_nf tmp_dl2 = (tmp_nf-2.5)/(2*abs(tmp_nf-2.5)) * 4/ tmp_nf Leff = tmp_l - 2*(DL0+tmp_dl1*DL1+tmp_dl2*DL2) ; ; --------- Gate network ------------------------------ C:CGDEXT n20 n10 C=CGDEXT0*tmp_w C:CGSEXT n20 n30 C=CGSEXT0*tmp_w R:RGATE n20 n21 + R=(0.333*RSHG*tmp_w/(tmp_l*tmp_nf*tmp_nf*ngcon^2)) Noise=1 L:LGATE i2 n20 L=LGATE0*tmp_w ; --------- Drain network ----------------------------- C:CDSEXT n10 n30 C=CDSEXT0*tmp_w L:LDRAIN i1 n10 L=LDRAIN0*tmp_w ; --------- Source network ----------------------------- L:LSOURCE i3 n30 L=LSOURCE0*tmp_w ; --------- Substrate network ------------------------- ; Diodes are for n-type MOS transistors hsim_diode_area:Djdb_area n12 n10 Area=tmp_ad hsim_diode_perim:Djdb_perim n12 n10 Area=tmp_pd hsim_diode_area:Djsb_area n32 n30 Area=tmp_as hsim_diode_perim:Djsb_perim n32 n30 Area=tmp_ps ; R:RBDB n12 n40 + R=abs(factor_even_odd*tmp_nf*DDBC*RSHB / tmp_w) Noise=1 R:RBSB n32 n40 + R=abs(factor_even_odd*tmp_nf*DSBC*RSHB / tmp_w) Noise=1 R:RBPD n12 n41 + R=abs(0.5*RSHB*(tmp_l+DGG) / tmp_w) Noise=1 R:RBPS n32 n41 + R=abs(0.5*RSHB*(tmp_l+DGG) / tmp_w) Noise=1 ; L:LBULK i4 n40 L=LBULK0*tmp_w ; ; --------- Ideal mos transistor ---------------------- tmp_nqsmod = $mpar(NQSMOD=0) tmp_acnqsmod = $mpar(ACNQSMOD=0) hsim2_mos:MAIN n10 n21 n30 n41 + Length=Leff Width=tmp_w/tmp_nf \ + Ad=tmp_ad/tmp_nf As=tmp_as/tmp_nf \ + Pd=tmp_pd/tmp_nf Ps=tmp_ps/tmp_nf \ + Nrd=tmp_nrd/tmp_nf Nrs=tmp_nrs/tmp_nf \ + Nqsmod=tmp_nqsmod Acnqsmod=tmp_acnqsmod _M=tmp_nf ; end hsim2_RF_Extract