Jason Yu's Unfinished Symphony


The soft vector processor is coded in Verilog HDL, and simulated using ModelSim. Currently we have no compiler for the processor, but we do have an assembler. All the assembly instructions can be found in the Vector ISA specification document. You can find the latest progress and source code of the project below.


Project Files

These files are preliminary versions of my project files, and should not be directly used or modified at this point. They are provided simply for preliminary evaluation purposes.

The processor uses Altera megafunctions from Stratix III family, and may not compile on other familities of FPGAs.


Known Problems

If you find any bugs/problems other than the ones listed here, please email me and tell me about them.


Change Log

Nov 2, 2008

May 9, 2008

Apr 26, 2008

Feb 23, 2008

Feb 8, 2008

Jan 8, 2008

Dec 28, 2007

Dec. 25, 2007


Most Likely Coming Soon


Future Improvements (probably not by me)




I would like to thank Chris Eagleston for developing the assembler for this architecture, Blair Fort for providing the UTIIe for this research, and Dr. Guy Lemieux for his guidance and supervision on this project. This research is partially funded by NSERC.

Last updated Nov 2, 2008. Copyright © 2007 Jason Yu. All rights reserved.