odin_ii.c File Reference

#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include "globals.h"
#include "types.h"
#include "util.h"
#include "netlist_utils.h"
#include "arch_types.h"
#include "parse_making_ast.h"
#include "netlist_create_from_ast.h"
#include "outputs.h"
#include "netlist_optimizations.h"
#include "ezxml.h"
#include "read_xml_arch_file.h"
#include "partial_map.h"
#include "multipliers.h"
#include "netlist_check.h"
#include "activity_estimation.h"
#include "high_level_data.h"
#include "hard_blocks.h"
#include "memories.h"
#include "errors.h"

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Functions
void	get_options (int argc, char **argv)
void	do_high_level_synthesis ()
void	do_simulation_of_netlist ()
void	do_activation_estimation (int num_types, t_type_descriptor *type_descriptors)
int	main (int argc, char **argv)
Variables
global_args_t	global_args
int	current_parse_file
t_arch	Arch
t_type_descriptor *	type_descriptors
int	block_tag
static const char *	optString = "hHc:V:h:o:O:a:B:N:f:s:S:g:G:t:T:"

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Function Documentation

void do_activation_estimation	(	int	num_types,
		t_type_descriptor *	type_descriptors
	)

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void do_high_level_synthesis

(

)

Definition at line 230 of file odin_ii.c.

{
        printf("--------------------------------------------------------------------\n");
        printf("High-level synthesis Begin\n");

        /* Perform any initialization routines here */
#ifdef VPR6
        find_hard_multipliers();
        register_hard_blocks();
#endif

        /* parse to abstract syntax tree */
        printf("Parser starting - we'll create an abstract syntax tree.  Note this tree can be viewed using GraphViz (see dosumentation)\n");
        parse_to_ast();
        /* Note that the entry point for ast optimzations is done per module with the function void next_parsed_verilog_file(ast_node_t *file_items_list) */

        /* after the ast is made potentiatlly do tagging for downstream links to verilog */
        if (global_args.high_level_block != NULL)
        {
                add_tag_data();
        }

        /* Now that we have a parse tree (abstract syntax tree [ast]) of the Verilog we want to make into a netlist. */
        printf("Converting AST into a Netlist - Note this netlist can be viewed using GraphViz (see dosumentation)\n");
        create_netlist();

        check_netlist(verilog_netlist); // can't levelize yet since the large muxes can look like combinational loops when they're not


        /* Report on Logical Memory usage */
        report_memory_distribution();

        /* point for all netlist optimizations. */
        printf("Performing Optimizations of the Netlist\n");
        netlist_optimizations_top(verilog_netlist);

        /* point where we convert netlist to FPGA or other hardware target compatible format */
        printf("Performing Partial Map to target device\n");
        partial_map_top(verilog_netlist);

        /* check for problems in the partial mapped netlist */
        printf("Check for liveness and combinational loops\n");
#ifdef VPR5
        levelize_and_check_for_combinational_loop_and_liveness(TRUE, verilog_netlist);
#endif

        /* point for outputs.  This includes soft and hard mapping all structures to the target format.  Some of these could be considred optimizations */
        printf("Outputting the netlist to the specified output format\n");
        output_top(verilog_netlist);

        printf("Successful High-level synthesis by Odin\n");
        printf("--------------------------------------------------------------------\n");
}

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void do_simulation_of_netlist

(

)

Definition at line 287 of file odin_ii.c.

{
        if (global_args.sim_type == NO_SIMULATION)
                return;
        printf("Netlist Simulation Begin\n");
        if (global_args.sim_type == GENERATE_VECTORS)
        {
                printf("Testing new (random) vectors.\n");
                simulate_new_vectors(global_args.num_test_vectors, verilog_netlist);
        }
        else //global_args.sim_type == TEST_EXISTING_VECTORS
        {
                printf("Testing existing vectors.\n");
                simulate_blif(global_args.sim_vectors_file, verilog_netlist);
        }
        printf("\n--------------------------------------------------------------------\n");
}

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void get_options	(	int	argc,
		char **	argv
	)

Definition at line 124 of file odin_ii.c.

{
        int opt = 0;

        /* set up the global arguments to there defualts */
        global_args.config_file = NULL;
        global_args.verilog_file = NULL;
        global_args.output_file = NULL;
        global_args.arch_file = NULL;
        global_args.activation_blif_file = NULL;
        global_args.activation_netlist_file = NULL;
        global_args.high_level_block = NULL;
        global_args.sim_vectors_file = NULL;
        global_args.sim_type = NO_SIMULATION;
        global_args.num_test_vectors = 0;

        /* set up the global configuration ahead of time */
        configuration.list_of_file_names = NULL;
        configuration.num_list_of_file_names = 0;
        configuration.output_type = "blif";
        configuration.output_ast_graphs = 0;
        configuration.output_netlist_graphs = 0;
        configuration.print_parse_tokens = 0;
        configuration.output_preproc_source = 0;
        configuration.debug_output_path = ".";
        configuration.arch_file = NULL;

        /* read in the option line */
        opt = getopt(argc, argv, optString);
        while(opt != -1) 
        {
                switch(opt) 
                {
                /* arch file */
                case 'a': 
                        global_args.arch_file = optarg;
                        configuration.arch_file = optarg;
                        break;
                /* config file */
                case 'c': 
                        global_args.config_file = optarg;
                        break;
                case 'V': 
                        global_args.verilog_file = optarg;
                        break;
                case 'o':
                case 'O':
                        global_args.output_file = optarg;
                        break;
                case 'B':
                        global_args.activation_blif_file = optarg;
                        break;
                case 'N':
                        global_args.activation_netlist_file = optarg;
                        break;
                case 'f':
#ifdef VPR5
                        global_args.high_level_block = optarg;
#endif
#ifdef VPR6
                        warning_message(0, -1, 0, "VPR 6.0 doesn't have this feature yet.  You'll need to deal with the output_blif.c differences wrapped by \"if (global_args.high_level_block != NULL)\"\n");
#endif
                        break;
                case 'h':
                case 'H':
                        printf("Usage: odin_II.exe\n\tOne of:\n\t\t-c <config_file_name.xml>\n\t\t-V <verilog_file_name.v>\n\tAlso options of:\n\t\t-o <output_path and file name>\n\t\t-a <architecture_file_in_VPR6.0_form>\n\t\t-B <blif_file_for_activation_estimation> -N <net_file_for_activation_estimation>\n\nSimulation options:\n\t\t -g <number_of_random_test_vectors\n\t\t -t test_vector_file\n");
                        exit(-1);
                        break;
                case 'g':
                case 'G':
                        global_args.num_test_vectors = atoi(optarg);
                        global_args.sim_type = GENERATE_VECTORS;
                        break;
                case 't':
                case 'T':
                        global_args.sim_vectors_file = optarg;
                        global_args.sim_type = TEST_EXISTING_VECTORS;
                        break;
                case 's':
                case 'S':
                        global_args.sim_vectors_file = optarg;
                        break;
                default : 
                        printf("Usage: \"odin_II.exe -h\" for usage\n");
                        exit(-1);
                        break;
                }

                opt = getopt(argc, argv, optString);
        }

        if ((global_args.config_file == NULL) && (global_args.verilog_file == NULL) && 
                        ((global_args.activation_blif_file == NULL) || (global_args.activation_netlist_file == NULL)))
        {
                printf("Error: must include either a activation blif and netlist file, a config file, or a verilog file\n");
                exit(-1);
        }
        else if ((global_args.config_file != NULL) && ((global_args.verilog_file != NULL) || (global_args.activation_blif_file != NULL)))
        {
                printf("Warning: Using command line options for verilog input file!!!\n");
        }
}

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int main	(	int	argc,
		char **	argv
	)

Definition at line 61 of file odin_ii.c.

{
        int num_types;
        int return_val = 0;

        printf("--------------------------------------------------------------------\n");
        printf("Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)\n");
        printf("Email: jamieson.peter@gmail.com and ken@unb.ca for support issues\n\n");

        /* get the command line options */
        get_options(argc, argv);

        /* read the confirguration file .. get options presets the config values just in case theyr'e not read in with config file */
        if (global_args.config_file != NULL)
        {
                printf("Reading Configuration file\n");
                read_config_file(global_args.config_file);
        }

        /* read the FPGA architecture file */
        if (global_args.arch_file != NULL)
        {
                printf("Reading FPGA Architecture file\n");
#ifdef VPR5
                t_clocks ClockDetails = { 0 };
                t_power PowerDetails = { 0 };
                XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types, &ClockDetails, &PowerDetails);
#endif
#ifdef VPR6
                XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types);
#endif
        }

        if (global_args.activation_blif_file != NULL && global_args.activation_netlist_file != NULL)
        {
#ifdef VPR5
                do_activation_estimation(num_types, type_descriptors);
#endif
                return_val = 1;
        }
        else
        {
                /* High level synthesis tool */
                do_high_level_synthesis();

                /* Simulate blif netlist */
                do_simulation_of_netlist();
        }

        /* activation estimation tool */

#ifdef VPR6
        report_mult_distribution();
        deregister_hard_blocks();
#endif

        return 0;
} 

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---

Variable Documentation

t_arch Arch

Definition at line 53 of file odin_ii.c.

int block_tag

Definition at line 55 of file odin_ii.c.

int current_parse_file

Definition at line 52 of file odin_ii.c.

global_args_t global_args

Definition at line 51 of file odin_ii.c.

const char* optString = "hHc:V:h:o:O:a:B:N:f:s:S:g:G:t:T:" [static]

Definition at line 120 of file odin_ii.c.

t_type_descriptor* type_descriptors

Definition at line 54 of file odin_ii.c.