partial_map.c File Reference

#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include "types.h"
#include "globals.h"
#include "errors.h"
#include "netlist_utils.h"
#include "node_creation_library.h"
#include "odin_util.h"
#include "outputs.h"
#include "partial_map.h"
#include "multipliers.h"
#include "util.h"
#include "hard_blocks.h"

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Functions
void	depth_first_traversal_to_partial_map (short marker_value, netlist_t *netlist)
void	depth_first_traverse_parital_map (nnode_t *node, int traverse_mark_number, netlist_t *netlist)
void	partial_map_node (nnode_t *node, short traverse_number, netlist_t *netlist)
void	instantiate_not_logic (nnode_t *node, short mark, netlist_t *netlist)
void	instantiate_buffer (nnode_t *node, short mark, netlist_t *netlist)
void	instantiate_bitwise_logic (nnode_t *node, operation_list op, short mark, netlist_t *netlist)
void	instantiate_bitwise_reduction (nnode_t *node, operation_list op, short mark, netlist_t *netlist)
void	instantiate_logical_logic (nnode_t *node, operation_list op, short mark, netlist_t *netlist)
void	instantiate_EQUAL (nnode_t *node, short type, short mark, netlist_t *netlist)
void	instantiate_GE (nnode_t *node, short type, short mark, netlist_t *netlist)
void	instantiate_GT (nnode_t *node, short type, short mark, netlist_t *netlist)
void	instantiate_shift_left_or_right (nnode_t *node, short type, short mark, netlist_t *netlist)
void	instantiate_multi_port_mux (nnode_t *node, short mark, netlist_t *netlist)
void	instantiate_add_w_carry (nnode_t *node, short mark, netlist_t *netlist)
void	instantiate_unary_sub (nnode_t *node, short mark, netlist_t *netlist)
void	instantiate_sub_w_carry (nnode_t *node, short mark, netlist_t *netlist)
void	partial_map_top (netlist_t *netlist)

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Function Documentation

void depth_first_traversal_to_partial_map	(	short	marker_value,
		netlist_t *	netlist
	)

Definition at line 74 of file partial_map.c.

{
        int i;

        /* start with the primary input list */
        for (i = 0; i < netlist->num_top_input_nodes; i++)
        {
                if (netlist->top_input_nodes[i] != NULL)
                {
                        depth_first_traverse_parital_map(netlist->top_input_nodes[i], marker_value, netlist);
                }
        }
        /* now traverse the ground and vcc pins */
        depth_first_traverse_parital_map(netlist->gnd_node, marker_value, netlist);
        depth_first_traverse_parital_map(netlist->vcc_node, marker_value, netlist);
}

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void depth_first_traverse_parital_map	(	nnode_t *	node,
		int	traverse_mark_number,
		netlist_t *	netlist
	)

Definition at line 94 of file partial_map.c.

{
        int i, j;
        nnode_t *next_node;
        nnet_t *next_net;

        if (node->traverse_visited == traverse_mark_number)
        {
                return;
        }
        else
        {
                /* ELSE - this is a new node so depth visit it */

                /* mark that we have visitied this node now */
                node->traverse_visited = traverse_mark_number;

                for (i = 0; i < node->num_output_pins; i++)
                {
                        if (node->output_pins[i]->net == NULL)
                                continue;

                        next_net = node->output_pins[i]->net;
                        for (j = 0; j < next_net->num_fanout_pins; j++)
                        {
                                if (next_net->fanout_pins[j] == NULL)
                                        continue;

                                next_node = next_net->fanout_pins[j]->node;
                                if (next_node == NULL)
                                        continue;

                                /* recursive call point */
                                depth_first_traverse_parital_map(next_node, traverse_mark_number, netlist);
                        }
                }

                /* POST traverse  map the node since you might delete */
                partial_map_node(node, traverse_mark_number, netlist);
        }
}

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void instantiate_add_w_carry	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 587 of file partial_map.c.

{
        int width;
        int width_a;
        int width_b;
        int i;
        nnode_t **new_add_cells;
        nnode_t **new_carry_cells;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        width = node->output_port_sizes[0];
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];

        new_add_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        new_carry_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);

        /* create the adder units and the zero unit */
        for (i = 0; i < width; i++)
        {
                new_add_cells[i] = make_3port_gate(ADDER_FUNC, 1, 1, 1, 1, node, mark);
                if (i < width - 1)
                {
                        new_carry_cells[i] = make_3port_gate(CARRY_FUNC, 1, 1, 1, 1, node, mark);
                }
        }

        /* ground first carry in */
        add_a_input_pin_to_node_spot_idx(new_add_cells[0], get_a_zero_pin(netlist), 0);
        if (i > 1)
        {
                add_a_input_pin_to_node_spot_idx(new_carry_cells[0], get_a_zero_pin(netlist), 0);
        }

        /* connect inputs */
        for(i = 0; i < width; i++)
        {
                if (i < width_a)
                {
                        /* join the A port up to adder */
                        remap_pin_to_new_node(node->input_pins[i], new_add_cells[i], 1);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], copy_input_npin(new_add_cells[i]->input_pins[1]), 1);
                }
                else 
                {
                        add_a_input_pin_to_node_spot_idx(new_add_cells[i], get_a_zero_pin(netlist), 1);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], get_a_zero_pin(netlist), 1);
                }

                if (i < width_b)
                {
                        /* join the B port up to adder */
                        remap_pin_to_new_node(node->input_pins[i+width_a], new_add_cells[i], 2);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], copy_input_npin(new_add_cells[i]->input_pins[2]), 2);
                }
                else
                {
                        add_a_input_pin_to_node_spot_idx(new_add_cells[i], get_a_zero_pin(netlist), 2);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], get_a_zero_pin(netlist), 2);
                }

                /* join that gate to the output */
                remap_pin_to_new_node(node->output_pins[i], new_add_cells[i], 0);
        }
        
        /* connect carry outs with carry ins */
        for(i = 1; i < width; i++)
        {
                connect_nodes(new_carry_cells[i-1], 0, new_add_cells[i], 0);
                if (i < width - 1)
                        connect_nodes(new_carry_cells[i-1], 0, new_carry_cells[i], 0);
        }

        free(new_add_cells);
        free(new_carry_cells);
}

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void instantiate_bitwise_logic	(	nnode_t *	node,
		operation_list	op,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 493 of file partial_map.c.

{
        int width;
        int i;
        int port_B_offset;
        int width_a;
        int width_b;
        nnode_t **new_logic_cells;
        operation_list cell_op;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        /* setup the calculations for padding and indexing */
        width = node->output_port_sizes[0];
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];
        port_B_offset = width_a;

        switch (op)
        {
                case BITWISE_AND:
                        cell_op = LOGICAL_AND;
                        break;
                case BITWISE_OR:
                        cell_op = LOGICAL_OR;
                        break;
                case BITWISE_NAND:
                        cell_op = LOGICAL_NAND;
                        break;
                case BITWISE_NOR:
                        cell_op = LOGICAL_NOR;
                        break;
                case BITWISE_XNOR:
                        cell_op = LOGICAL_XNOR;
                        break;
                case BITWISE_XOR:
                        cell_op = LOGICAL_XOR;
                        break;
                default:
                        oassert(FALSE);
                        break;
        }
        new_logic_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        for (i = 0; i < width; i++)
        {
                /* instantiate the cells */
                new_logic_cells[i] = make_2port_gate(cell_op, 1, 1, 1, node, mark);
        }

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        if (i < width_b)
                        {
                                /* IF - this current input will also have a corresponding b_port input then join it to the gate */
                                remap_pin_to_new_node(node->input_pins[i], new_logic_cells[i], 0);
                        }
                        else
                        {
                                /* ELSE - the B input does not exist, so this answer goes right through */
                                add_a_input_pin_to_node_spot_idx(new_logic_cells[i], get_a_zero_pin(netlist), 0);
                        }
                }

                if (i < width_b)
                {
                        if (i < width_a)
                        {
                                /* IF - this current input will also have a corresponding a_port input then join it to the gate */
                                /* Joining the inputs to the input 2 of that gate */
                                remap_pin_to_new_node(node->input_pins[i+port_B_offset], new_logic_cells[i], 1);
                        }
                        else
                        {
                                /* ELSE - the A input does not exist, so this answer goes right through */
                                add_a_input_pin_to_node_spot_idx(new_logic_cells[i], get_a_zero_pin(netlist), 1);
                        }
                }

                remap_pin_to_new_node(node->output_pins[i], new_logic_cells[i], 0);
        }

        free(new_logic_cells);
}

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void instantiate_bitwise_reduction	(	nnode_t *	node,
		operation_list	op,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 424 of file partial_map.c.

{
        int width;
        int i;
        int width_a;
        nnode_t *new_logic_cell;
        operation_list cell_op;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 1);
        oassert(node->output_port_sizes[0] == 1);
        /* setup the calculations for padding and indexing */
        width = node->output_port_sizes[0];
        width_a = node->input_port_sizes[0];

        switch (op)
        {
                case BITWISE_AND:
                case LOGICAL_AND:
                        cell_op = LOGICAL_AND;
                        break;
                case BITWISE_OR:
                case LOGICAL_OR:
                        cell_op = LOGICAL_OR;
                        break;
                case BITWISE_NAND:
                case LOGICAL_NAND:
                        cell_op = LOGICAL_NAND;
                        break;
                case BITWISE_NOR:
                case LOGICAL_NOR:
                        cell_op = LOGICAL_NOR;
                        break;
                case BITWISE_XNOR:
                case LOGICAL_XNOR:
                        cell_op = LOGICAL_XNOR;
                        break;
                case BITWISE_XOR:
                case LOGICAL_XOR:
                        cell_op = LOGICAL_XOR;
                        break;
                default:
                        oassert(FALSE);
        }
        /* instantiate the cells */
        new_logic_cell = make_1port_logic_gate(cell_op, width_a, node, mark);

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width_a; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        remap_pin_to_new_node(node->input_pins[i], new_logic_cell, i);
                }
                else
                {
                        /* ELSE - the B input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(new_logic_cell, get_a_zero_pin(netlist), i);
                }
        }

        remap_pin_to_new_node(node->output_pins[0], new_logic_cell, 0);
}

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void instantiate_buffer	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 340 of file partial_map.c.

{
        int width = node->num_input_pins;
        int i;

        /* for now we just pass the signals dierectly through */
        for (i = 0; i < width; i++)
        {
                int idx_2_buffer = node->input_pins[i]->pin_net_idx;

                /* join all fanouts of the output net with the input pins net */
                join_nets(node->input_pins[i]->net, node->output_pins[i]->net);

                /* erase the pointer to this buffer */
                node->input_pins[i]->net->fanout_pins[idx_2_buffer] = NULL;
        }
}

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void instantiate_EQUAL	(	nnode_t *	node,
		short	type,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 834 of file partial_map.c.

{
        int width_a;
        int width_b;
        int width_max;
        int i;
        int port_B_offset;
        nnode_t *xnor_gate;
        nnode_t *logical_and_gate;

        oassert(node->num_output_pins == 1);
        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];
        width_max = width_a > width_b ? width_a : width_b;
        port_B_offset = width_a;

        /* build an xnor bitwise XNOR */
        xnor_gate = make_2port_gate(LOGICAL_XNOR, width_a, width_b, width_max, node, mark);
        /* build an and bitwise AND */
        logical_and_gate = make_1port_logic_gate(LOGICAL_AND, width_max, node, mark);

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width_max; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        if (i < width_b)
                        {
                                /* IF - this current input will also have a corresponding b_port input then join it to the gate */
                                remap_pin_to_new_node(node->input_pins[i], xnor_gate, i);
                        }
                        else
                        {
                                /* ELSE - the B input does not exist, so this answer goes right through */
                                add_a_input_pin_to_node_spot_idx(xnor_gate, get_a_zero_pin(netlist), i);
                        }
                }

                if (i < width_b)
                {
                        if (i < width_a)
                        {
                                /* IF - this current input will also have a corresponding a_port input then join it to the gate */
                                /* Joining the inputs to the input 2 of that gate */
                                remap_pin_to_new_node(node->input_pins[i+port_B_offset], xnor_gate, i+port_B_offset);
                        }
                        else
                        {
                                /* ELSE - the A input does not exist, so this answer goes right through */
                                add_a_input_pin_to_node_spot_idx(xnor_gate, get_a_zero_pin(netlist), i+port_B_offset);
                        }
                }

                /* hook it up to the logcial AND */
                connect_nodes(xnor_gate, i, logical_and_gate, i);
        }

        /* join that gate to the output */
        remap_pin_to_new_node(node->output_pins[0], logical_and_gate, 0);

        if (type == LOGICAL_EQUAL)
                instantiate_bitwise_logic(xnor_gate, BITWISE_XNOR, mark, netlist);
        else if (type == NOT_EQUAL)
                instantiate_bitwise_logic(xnor_gate, BITWISE_XOR, mark, netlist);
        /* Don't need to instantiate a Logic and gate since it is a function itself */

        oassert(logical_and_gate->num_output_pins == 1);
}

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void instantiate_GE	(	nnode_t *	node,
		short	type,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 1050 of file partial_map.c.

{
        int width_a;
        int width_b;
        int width_max;
        int i;
        int port_B_offset;
        int port_A_offset;
        nnode_t *equal;
        nnode_t *gt;
        nnode_t *logical_or_final_gate;

        oassert(node->num_output_pins == 1);
        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        oassert(node->input_port_sizes[0] == node->input_port_sizes[1]);
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];
        oassert(width_a == width_b);
        width_max = width_a > width_b ? width_a : width_b;

        /* swaps ports A and B */
        if (type == GTE)
        {
                port_A_offset = 0;
                port_B_offset = width_a;
        }
        else if (type == LTE)
        {
                port_A_offset = width_b;
                port_B_offset = 0;
        }

        /* build an xnor bitwise XNOR */
        equal = make_2port_gate(LOGICAL_EQUAL, width_a, width_b, 1, node, mark);
        gt = make_2port_gate(GT, width_a, width_b, 1, node, mark);
        logical_or_final_gate = make_1port_logic_gate(LOGICAL_OR, 2, node, mark);

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width_max; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        /* IF - this current input will also have a corresponding b_port input then join it to the gate */
                        remap_pin_to_new_node(node->input_pins[i+port_A_offset], equal, i+port_A_offset);
                        add_a_input_pin_to_node_spot_idx(gt, copy_input_npin(equal->input_pins[i+port_A_offset]), i+port_A_offset);
                }
                else
                {
                        /* ELSE - the B input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(equal, get_a_zero_pin(netlist), i+port_A_offset);
                        add_a_input_pin_to_node_spot_idx(gt, get_a_zero_pin(netlist), i+port_A_offset);
                }

                if (i < width_b)
                {
                        /* IF - this current input will also have a corresponding a_port input then join it to the gate */
                        /* Joining the inputs to the input 2 of that gate */
                        remap_pin_to_new_node(node->input_pins[i+port_B_offset], equal, i+port_B_offset);
                        add_a_input_pin_to_node_spot_idx(gt, copy_input_npin(equal->input_pins[i+port_B_offset]), i+port_B_offset);
                }
                else
                {
                        /* ELSE - the A input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(equal, get_a_zero_pin(netlist), i+port_B_offset);
                        add_a_input_pin_to_node_spot_idx(gt, get_a_zero_pin(netlist), i+port_B_offset);
                }
        }
        connect_nodes(equal, 0, logical_or_final_gate, 0);
        connect_nodes(gt, 0, logical_or_final_gate, 1);

        /* join that gate to the output */
        remap_pin_to_new_node(node->output_pins[0], logical_or_final_gate, 0);
        oassert(logical_or_final_gate->num_output_pins == 1);

        /* make the two intermediate gates */
        instantiate_EQUAL(equal, LOGICAL_EQUAL, mark, netlist);
        instantiate_GT(gt, GT, mark, netlist);
}

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void instantiate_GT	(	nnode_t *	node,
		short	type,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 911 of file partial_map.c.

{
        int width_a;
        int width_b;
        int width_max;
        int i;
        int port_A_offset;
        int port_B_offset;
        int port_A_index;
        int port_B_index;
        int index = 0;
        nnode_t *xor_gate;
        nnode_t *logical_or_gate;
        nnode_t **or_cells;
        nnode_t **gt_cells;

        oassert(node->num_output_pins == 1);
        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        oassert(node->input_port_sizes[0] == node->input_port_sizes[1]);
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];
        width_max = width_a > width_b ? width_a : width_b;

        /* swaps ports A and B */
        if (type == GT)
        {
                port_A_offset = 0;
                port_B_offset = width_a;
                port_A_index = 0;
                port_B_index = width_a-1;
        }
        else if (type == LT)
        {
                port_A_offset = width_b;
                port_B_offset = 0;
                port_A_index = width_b-1;
                port_B_index = 0;
        }

        /* xor gate identifies if any bits don't match */
        xor_gate = make_2port_gate(LOGICAL_XOR, width_a-1, width_b-1, width_max-1, node, mark);
        /* collects all the GT signals and determines if gt */
        logical_or_gate = make_1port_logic_gate(LOGICAL_OR, width_max, node, mark);
        /* collects a chain if any 1 happens than the GT cells output 0 */
        or_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width_max-1);
        /* each cell checks if A > B and sends out a 1 if history has no 1s (3rd input) */
        gt_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width_max);

        for (i = 0; i < width_max; i++)
        {
                gt_cells[i] = make_3port_gate(GT, 1, 1, 1, 1, node, mark);
                if (i < width_max-1)
                {
                        or_cells[i] = make_2port_gate(LOGICAL_OR, 1, 1, 1, node, mark);
                }
        }

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width_max; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        /* IF - this current input will also have a corresponding b_port input then join it to the gate */
                        remap_pin_to_new_node(node->input_pins[i+port_A_offset], gt_cells[i], 0);
                        if (i > 0)
                                add_a_input_pin_to_node_spot_idx(xor_gate, copy_input_npin(gt_cells[i]->input_pins[0]), index+port_A_index);
                }
                else
                {
                        /* ELSE - the B input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(gt_cells[i], get_a_zero_pin(netlist), 0);
                        if (i > 0)
                                add_a_input_pin_to_node_spot_idx(xor_gate, get_a_zero_pin(netlist), index+port_A_index);
                }

                if (i < width_b)
                {
                        /* IF - this current input will also have a corresponding a_port input then join it to the gate */
                        /* Joining the inputs to the input 2 of that gate */
                        remap_pin_to_new_node(node->input_pins[i+port_B_offset], gt_cells[i], 1);
                        if (i > 0)
                                add_a_input_pin_to_node_spot_idx(xor_gate, copy_input_npin(gt_cells[i]->input_pins[1]), index+port_B_index);
                }
                else
                {
                        /* ELSE - the A input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(gt_cells[i], get_a_zero_pin(netlist), 1);
                        if (i > 0)
                                add_a_input_pin_to_node_spot_idx(xor_gate, get_a_zero_pin(netlist), index+port_B_index);
                }

                if (i < width_max-1)
                {
                        /* number of OR gates */
                        if (i < width_max-2)
                        {
                                /* connect the msb or to the next lower bit */
                                connect_nodes(or_cells[i+1], 0, or_cells[i], 1);
                        }
                        else
                        {
                                /* deal with the first greater than test which autom gets a zero */
                                add_a_input_pin_to_node_spot_idx(or_cells[i], get_a_zero_pin(netlist), 1);
                        }

                        /* get all the equals with the or gates */
                        connect_nodes(xor_gate, i, or_cells[i], 0);
                        connect_nodes(or_cells[i], 0, gt_cells[i], 2);
                        
                }
                else
                {
                        /* deal with the first greater than test which autom gets a zero */
                        add_a_input_pin_to_node_spot_idx(gt_cells[i], get_a_zero_pin(netlist), 2);
                }

                /* hook it up to the logcial AND */
                connect_nodes(gt_cells[i], 0, logical_or_gate, i);

                if (i > 0)
                {
                        index++;
                }
        }

        /* join that gate to the output */
        remap_pin_to_new_node(node->output_pins[0], logical_or_gate, 0);
        oassert(logical_or_gate->num_output_pins == 1);

        instantiate_bitwise_logic(xor_gate, BITWISE_XOR, mark, netlist);
}

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void instantiate_logical_logic	(	nnode_t *	node,
		operation_list	op,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 361 of file partial_map.c.

{
        int i;
        int port_B_offset;
        int width_a;
        int width_b;
        nnode_t *new_logic_cell;
        nnode_t *reduction1;
        nnode_t *reduction2;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        oassert(node->num_output_pins == 1);
        /* setup the calculations for padding and indexing */
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];
        port_B_offset = width_a;

        /* instantiate the cells */
        new_logic_cell = make_1port_logic_gate(op, 2, node, mark);
        reduction1 = make_1port_logic_gate(BITWISE_OR, width_a, node, mark);
        reduction2 = make_1port_logic_gate(BITWISE_OR, width_b, node, mark);

        /* connect inputs.  In the case that a signal is smaller than the other then zero pad */
        for(i = 0; i < width_a; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_a)
                {
                        remap_pin_to_new_node(node->input_pins[i], reduction1, i);
                }
                else
                {
                        /* ELSE - the B input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(reduction1, get_a_zero_pin(netlist), i);
                }
        }
        for(i = 0; i < width_b; i++)
        {
                /* Joining the inputs to the input 1 of that gate */
                if (i < width_b)
                {
                        remap_pin_to_new_node(node->input_pins[i+port_B_offset], reduction2, i);
                }
                else
                {
                        /* ELSE - the B input does not exist, so this answer goes right through */
                        add_a_input_pin_to_node_spot_idx(reduction2, get_a_zero_pin(netlist), i);
                }
        }

        connect_nodes(reduction1, 0, new_logic_cell, 0);
        connect_nodes(reduction2, 0, new_logic_cell, 1);

        instantiate_bitwise_reduction(reduction1, BITWISE_OR, mark, netlist);
        instantiate_bitwise_reduction(reduction2, BITWISE_OR, mark, netlist);

        remap_pin_to_new_node(node->output_pins[0], new_logic_cell, 0);
}

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void instantiate_multi_port_mux	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 263 of file partial_map.c.

{
        int i, j;
        int width_of_one_hot_logic;
        int num_ports;
        int port_offset;
        nnode_t **muxes;
        
        /* setup the calculations for padding and indexing */
        width_of_one_hot_logic = node->input_port_sizes[0];
        num_ports = node->num_input_port_sizes;
        port_offset = node->input_port_sizes[1];

        muxes = (nnode_t**)malloc(sizeof(nnode_t*)*(num_ports-1));
        for(i = 0; i < num_ports-1; i++)
        {
                muxes[i] = make_2port_gate(MUX_2, width_of_one_hot_logic, width_of_one_hot_logic, 1, node, mark);
        }

        for(j = 0; j < num_ports - 1; j++)
        {
                if (j == 0)
                {
                        for(i = 0; i < width_of_one_hot_logic; i++)
                        {
                                /* map the inputs to the muxt */
                                remap_pin_to_new_node(node->input_pins[i+(j+1)*port_offset], muxes[j], width_of_one_hot_logic+i);
                                /* map the one hot logic control */
                                remap_pin_to_new_node(node->input_pins[i], muxes[j], i);
                        }
                }
                else
                {
                        for(i = 0; i < width_of_one_hot_logic; i++)
                        {
                                /* map the inputs to the muxt */
                                remap_pin_to_new_node(node->input_pins[i+(j+1)*port_offset], muxes[j], width_of_one_hot_logic+i);
                                /* map the one hot logic control */
                                add_a_input_pin_to_node_spot_idx(muxes[j], copy_input_npin(muxes[0]->input_pins[i]), i);
                        }
                }
                /* now hookup outputs */
                remap_pin_to_new_node(node->output_pins[j], muxes[j], 0);
        }
}

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void instantiate_not_logic	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 312 of file partial_map.c.

{
        int width = node->num_input_pins;
        nnode_t **new_not_cells;
        int i;

        new_not_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);

        for (i = 0; i < width; i++)
        {
                new_not_cells[i] = make_not_gate(node, mark);
        }

        /* connect inputs and outputs */
        for(i = 0; i < width; i++)
        {
                /* Joining the inputs to the new soft NOT GATES */
                remap_pin_to_new_node(node->input_pins[i], new_not_cells[i], 0);
                remap_pin_to_new_node(node->output_pins[i], new_not_cells[i], 0);
        }

        free(new_not_cells);
}

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void instantiate_shift_left_or_right	(	nnode_t *	node,
		short	type,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 1135 of file partial_map.c.

{
        /* these variables are used in an attempt so that I don't need if cases.  Probably a bad idea, but fun */
        int width;
        int i;
        int shift_size;
        nnode_t *buf_node;

        width = node->input_port_sizes[0];

        if (node->related_ast_node->children[1]->type == NUMBERS)
        {
                /* record the size of the shift */
                shift_size = node->related_ast_node->children[1]->types.number.value;
        }
        else
        {
                error_message(NETLIST_ERROR, node->related_ast_node->line_number, node->related_ast_node->file_number, "Odin only supports constant shifts at present\n");
        }       

        buf_node = make_1port_gate(BUF_NODE, width, width, node, mark);

        if (type == SL) 
        {
                /* IF shift left */

                /* connect inputs to outputs */
                for(i = 0; i < width - shift_size; i++)
                {
                        // connect higher output pin to lower input pin
                        remap_pin_to_new_node(node->input_pins[i], buf_node, i+shift_size);
                }
        
                /* connect ZERO to outputs that don't have inputs connected */
                for(i = 0; i < shift_size; i++)
                {
                        // connect 0 to lower outputs
                        add_a_input_pin_to_node_spot_idx(buf_node, get_a_zero_pin(netlist), i);
                }
        
                for(i = width-1; i >= width-shift_size; i--)
                {
                        /* demap the node from the net */
                        int idx_2_buffer = node->input_pins[i]->pin_net_idx;
                        node->input_pins[i]->net->fanout_pins[idx_2_buffer] = NULL;
                }
        }
        else
        {
                /* ELSE shift right */

                /* connect inputs to outputs */
                for(i = width - 1; i >= shift_size; i--)
                {
                        // connect higher input pin to lower output pin
                        remap_pin_to_new_node(node->input_pins[i], buf_node, i-shift_size);
                }
        
                /* connect ZERO to outputs that don't have inputs connected */
                for(i = width - 1; i >= width - shift_size; i--)
                {
                        // connect 0 to lower outputs
                        add_a_input_pin_to_node_spot_idx(buf_node, get_a_zero_pin(netlist), i);
                }
                for(i = 0; i < shift_size; i++)
                {
                        /* demap the node from the net */
                        int idx_2_buffer = node->input_pins[i]->pin_net_idx;
                        node->input_pins[i]->net->fanout_pins[idx_2_buffer] = NULL;
                }
        }

        for(i = 0; i < width; i++)
        {
                remap_pin_to_new_node(node->output_pins[i], buf_node, i);
        }
        /* instantiate the buffer */
        instantiate_buffer(buf_node, mark, netlist);
}

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void instantiate_sub_w_carry	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 674 of file partial_map.c.

{
        int width;
        int width_a;
        int width_b;
        int i;
        nnode_t **new_add_cells;
        nnode_t **new_carry_cells;
        nnode_t **new_not_cells;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 2);
        width = node->output_port_sizes[0];
        width_a = node->input_port_sizes[0];
        width_b = node->input_port_sizes[1];

        new_add_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        new_carry_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        new_not_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);

        /* create the adder units and the zero unit */
        for (i = 0; i < width; i++)
        {
                new_add_cells[i] = make_3port_gate(ADDER_FUNC, 1, 1, 1, 1, node, mark);
                new_not_cells[i] = make_not_gate(node, mark);
                if (i < width - 1)
                {
                        new_carry_cells[i] = make_3port_gate(CARRY_FUNC, 1, 1, 1, 1, node, mark);
                }
        }

        /* ground first carry in .  Note the one constant is inputted to start 2's complement */
        add_a_input_pin_to_node_spot_idx(new_add_cells[0], get_a_one_pin(netlist), 0);
        if (i > 1)
        {
                add_a_input_pin_to_node_spot_idx(new_carry_cells[0], get_a_one_pin(netlist), 0);
        }

        /* connect inputs */
        for(i = 0; i < width; i++)
        {
                if (i < width_a)
                {
                        /* join the A port up to adder */
                        remap_pin_to_new_node(node->input_pins[i], new_add_cells[i], 1);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], copy_input_npin(new_add_cells[i]->input_pins[1]), 1);
                }
                else
                {
                        add_a_input_pin_to_node_spot_idx(new_add_cells[i], get_a_zero_pin(netlist), 1);
                        if (i < width - 1)
                                add_a_input_pin_to_node_spot_idx(new_carry_cells[i], get_a_zero_pin(netlist), 1);
                }

                if (i < width_b)
                {
                        /* join the B port up to adder */
                        remap_pin_to_new_node(node->input_pins[i+width_a], new_not_cells[i], 0);
                }
                else 
                {
                        add_a_input_pin_to_node_spot_idx(new_not_cells[i], get_a_zero_pin(netlist), 0);
                }

                /* now hookup not to adder parts */
                connect_nodes(new_not_cells[i], 0, new_add_cells[i], 2);
                if (i < width - 1)
                        connect_nodes(new_not_cells[i], 0, new_carry_cells[i], 2);

                /* join that gate to the output */
                remap_pin_to_new_node(node->output_pins[i], new_add_cells[i], 0);
        }
        
        /* connect carry outs with carry ins */
        for(i = 1; i < width; i++)
        {
                connect_nodes(new_carry_cells[i-1], 0, new_add_cells[i], 0);
                if (i < width - 1)
                        connect_nodes(new_carry_cells[i-1], 0, new_carry_cells[i], 0);
        }

        free(new_add_cells);
        free(new_carry_cells);
}

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void instantiate_unary_sub	(	nnode_t *	node,
		short	mark,
		netlist_t *	netlist
	)

Definition at line 764 of file partial_map.c.

{
        int width;
        int width_a;
        int i;
        nnode_t **new_add_cells;
        nnode_t **new_carry_cells;
        nnode_t **new_not_cells;

        oassert(node->num_input_pins > 0);
        oassert(node->num_input_port_sizes == 1);
        width = node->output_port_sizes[0];
        width_a = node->input_port_sizes[0];

        new_add_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        new_carry_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);
        new_not_cells = (nnode_t**)malloc(sizeof(nnode_t*)*width);

        /* create the adder units and the zero unit */
        for (i = 0; i < width; i++)
        {
                new_add_cells[i] = make_3port_gate(ADDER_FUNC, 1, 1, 1, 1, node, mark);
                new_not_cells[i] = make_not_gate(node, mark);
                if (i < width - 1)
                {
                        new_carry_cells[i] = make_3port_gate(CARRY_FUNC, 1, 1, 1, 1, node, mark);
                }
        }

        /* ground first carry in .  Note the one constant is inputted to start 2's complement */
        add_a_input_pin_to_node_spot_idx(new_add_cells[0], get_a_one_pin(netlist), 0);
        if (i > 1)
        {
                add_a_input_pin_to_node_spot_idx(new_carry_cells[0], get_a_one_pin(netlist), 0);
        }

        /* connect inputs */
        for(i = 0; i < width; i++)
        {
                /* join the A port up to adder */
                remap_pin_to_new_node(node->input_pins[i], new_not_cells[i], 0);
                connect_nodes(new_not_cells[i], 0, new_add_cells[i], 1);
                if (i < width - 1)
                        connect_nodes(new_not_cells[i], 0, new_carry_cells[i], 1);

                add_a_input_pin_to_node_spot_idx(new_add_cells[i], get_a_zero_pin(netlist), 2);
                if (i < width - 1)
                        add_a_input_pin_to_node_spot_idx(new_carry_cells[i], get_a_zero_pin(netlist), 2);

                /* join that gate to the output */
                remap_pin_to_new_node(node->output_pins[i], new_add_cells[i], 0);
        }
        
        /* connect carry outs with carry ins */
        for(i = 1; i < width; i++)
        {
                connect_nodes(new_carry_cells[i-1], 0, new_add_cells[i], 0);
                if (i < width - 1)
                        connect_nodes(new_carry_cells[i-1], 0, new_carry_cells[i], 0);
        }

        free(new_add_cells);
        free(new_carry_cells);
}

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void partial_map_node	(	nnode_t *	node,
		short	traverse_number,
		netlist_t *	netlist
	)

Definition at line 139 of file partial_map.c.

{
        switch (node->type) 
        {
                case BITWISE_NOT:
                        instantiate_not_logic(node, traverse_number, netlist);
                        break;
                case BUF_NODE:
                        instantiate_buffer(node, traverse_number, netlist);
                        break;

                case BITWISE_AND:
                case BITWISE_OR:
                case BITWISE_NAND:
                case BITWISE_NOR:
                case BITWISE_XNOR:
                case BITWISE_XOR:
                        if (node->num_input_port_sizes == 2)
                        {
                                instantiate_bitwise_logic(node, node->type, traverse_number, netlist);
                        }
                        else if (node->num_input_port_sizes == 1)
                        {
                                instantiate_bitwise_reduction(node, node->type, traverse_number, netlist);
                        }
                        else    
                                oassert(FALSE);
                        break;

                case LOGICAL_OR:
                case LOGICAL_AND:
                case LOGICAL_NOR:
                case LOGICAL_NAND:
                case LOGICAL_XOR:
                case LOGICAL_XNOR:
                        if (node->num_input_port_sizes == 2)
                        {
                                instantiate_logical_logic(node, node->type, traverse_number, netlist);
                        }
                        break;

                case LOGICAL_NOT:
                        /* don't need to do anything since this is a reduction */
                        break;

                case ADD:
                        instantiate_add_w_carry(node, traverse_number, netlist);
                        break;
                case MINUS:
                        if (node->num_input_port_sizes == 2)
                        {
                                instantiate_sub_w_carry(node, traverse_number, netlist);
                        }
                        else if (node->num_input_port_sizes == 1)
                        {
                                instantiate_unary_sub(node, traverse_number, netlist);
                        }
                        else
                                oassert(FALSE);
                        break;
                case LOGICAL_EQUAL:
                case NOT_EQUAL:
                        instantiate_EQUAL(node, node->type, traverse_number, netlist);
                        break;
                case GTE:
                case LTE:
                        instantiate_GE(node, node->type, traverse_number, netlist);
                        break;
                case GT:
                case LT:
                        instantiate_GT(node, node->type, traverse_number, netlist);
                        break;
                case SL:
                case SR:
                        instantiate_shift_left_or_right(node, node->type, traverse_number, netlist);
                        break;
                case MULTI_PORT_MUX:
                        instantiate_multi_port_mux(node, traverse_number, netlist);
                        break;
                case MULTIPLY:
                        if (hard_multipliers != NULL)
                        {
#ifdef VPR6
                                if ((node->input_port_sizes[0] * node->input_port_sizes[1]) > min_mult)
                                        instantiate_hard_multiplier(node, traverse_number, netlist);
#endif
                        }
                        else
                                instantiate_simple_soft_multiplier(node, traverse_number, netlist);
                        break;
                
                case MEMORY:
                case HARD_IP:
#ifdef VPR6
                        instantiate_hard_block(node, traverse_number, netlist);
#endif
                        break;

                case ADDER_FUNC:
                case CARRY_FUNC:
                case MUX_2:
                case INPUT_NODE:
                case CLOCK_NODE:
                case OUTPUT_NODE:
                case GND_NODE:
                case VCC_NODE:
                case FF_NODE:
                        /* some nodes already in the form that is mapable */
                        break;

                case CASE_EQUAL:
                case CASE_NOT_EQUAL:
                case DIVIDE:
                case MODULO:
                default:
                        oassert(FALSE);
                        break;
        }
}

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void partial_map_top

(

netlist_t *

netlist

)

Definition at line 61 of file partial_map.c.

{
        /* depending on the output target choose how to do partial mapping */
        if (strcmp(configuration.output_type, "blif") == 0)
        {
                /* do the partial map without any larger structures identified */
                depth_first_traversal_to_partial_map(PARTIAL_MAP_TRAVERSE_VALUE, netlist);      
        }
}

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