ASG4: Question 3

Shereen Pang (shereen@interchange.ubc.ca) Wed, 29 Nov 2000 10:39:21 -1200 

Date: Wed, 29 Nov 2000 10:39:21 -1200
From: Shereen Pang <shereen@interchange.ubc.ca>
Subject: ASG4: Question 3



Hi, just want to clarify: in CPU write cycle, is t41 a propagation
delay? The reason why I think so is because BLE is measured to WR*,
which I assume is an output signal because of the diagram on the
assignment sheet.

Thanks

Shereen