Memory woes

Rustam Dhaliwal (rdhaliwa@interchange.ubc.ca) Wed, 29 Nov 2000 11:02:03 -0800 (PST) 

Date: Wed, 29 Nov 2000 11:02:03 -0800 (PST)
From: Rustam Dhaliwal <rdhaliwa@interchange.ubc.ca>
Subject: Memory woes



Dear Ed,

Is it just me or is Q1 buggered up good. Lets take the ROM for example. It
has 16k and in order to address 16k we need 14 pins (ideally this would be
A13-0 of the address bus). But since there is no A0 on the address bus,
we would then have to use A14-1. But is we did this the two 16k block
would not be in a contiguous range of memory. Can you help me Ed?