Re: ASG4: Question 3

Ed Casas (edc@ece.ubc.ca) Wed, 29 Nov 2000 12:54:22 -0800 

Date: Wed, 29 Nov 2000 12:54:22 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: ASG4: Question 3



> Hi, just want to clarify: in CPU write cycle, is t41 a
> propagation delay? The reason why I think so is because BLE is
> measured to WR*, which I assume is an output signal because of
> the diagram on the assignment sheet.

t41 is indeed a guaranteed response.  It might not be quite
accurate to call it a propagation delay because it's measured
between two outputs.  And you can't really call it a pulse width
because it measured between two different outputs.

This particular "propagation delay" is due to the two outputs
being generated by two circuits in the CPU that have different
propagation delays relative to the start of a bus cycle.  So t41
is really a difference of two propagation delays.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592